CYWUSB6935-28SEI Cypress Semiconductor Corp, CYWUSB6935-28SEI Datasheet - Page 14

• Manufacturer Part Number: CYWUSB6935-28SEI
• Description: IC WIRELESS USB 2.4GHZ 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYWUSB6935-28SEI

• Frequency: 2.4GHz
• Data Rate - Maximum: 62.5kbps
• Modulation Or Protocol: DSSS, GFSK
• Applications: AMR, ISM, RKE
• Power - Output: 0dBm
• Sensitivity: -95dBm
• Voltage - Supply: 2.7 V ~ 3.6 V
• Current - Receiving: 57.7mA
• Current - Transmitting: 69.1mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Memory Size: -
• Other names: 428-1576-5

Document 38-16008 Rev. **
Bit
7:0
Bit
7:0 Valid
Bit
7:0
Bit
7:0
Name
Name
Data
Name Description
Valid
Name
Data
7
7
7
7
Addr: 0x0A
Addr: 0x0B
Addr: 0x0C
Addr: 0x09
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C).The over-the-
air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed
by bit 6, followed by bit 7. This register is read-only.
Description
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Description
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A
register (Reg 0x09) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0A). The
over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5,
followed by bit 6, followed by bit 7. This register is read-only.
Description
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
6
6
6
6
5
5
5
5
Figure 7-11. Receive SERDES Valid A
Figure 7-13. Receive SERDES Valid B
Figure 7-10. Receive SERDES Data A
Figure 7-12. Receive SERDES Data B
PRELIMINARY
REG_RX_VALID_A
REG_RX_VALID_B
REG_RX_DATA_A
REG_RX_DATA_B
4
4
4
4
Data
Valid
Data
Valid
3
3
3
3
2
2
2
2
1
1
1
1
CYWUSB6935
Default: 0x00
Default: 0x00
Default: 0x00
Default: 0x00
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0
0
0
0