TRC101 RFM, TRC101 Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/5/563/rfm_sml.jpg)
TRC101
Manufacturer Part Number
TRC101
Description
RFIC TRANCEIVER MULTI-CHANNEL FS
Manufacturer
RFM
Series
TRCr
Datasheet
1.DR-TRC101-315-DK.pdf
(42 pages)
Specifications of TRC101
Frequency
300MHz ~ 1GHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK
Applications
General Purpose
Power - Output
8dBm
Sensitivity
-105dBm
Voltage - Supply
2.2 V ~ 5.4 V
Current - Receiving
17mA
Current - Transmitting
28mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory Size
-
Other names
583-1093-2
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
TRC101
Manufacturer:
FREESCALE
Quantity:
310
Part Number:
TRC101
Manufacturer:
RFM
Quantity:
20 000
Duty Cycle Set Register
The duty cycle register may be used in conjunction with the wake-up timer to reduce the average current
consumption of the receiver. The duty cycle register may be set up so that when the wake-up timer
brings the chip out of sleep mode the receiver is turned on for a short time to sample if a signal is present
and then goes back into sleep and the process starts over.
The duty cycle uses the Multiplier value of the wake-up timer in part for its calculation. To calculate the
duty cycle use:
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the Duty Cycle Set Register.
Bit [7..1] – Duty Cycle Multiplier: These bits are the decimal value used to calculate the Duty Cycle or
“On time” of the Receiver after the wake-up timer has brought the TRC101 out of sleep mode.
Bit [0] – Duty Cycle Mode Enable: This bit enables the duty cycle mode when set.
NOTE: The receiver must be disabled (RXEN = ‘0’ in Power Management Register) and the wake-up
timer must be enabled (WKUPEN = ‘1’ in Power Management Register) for operation in this mode.
www.RFM.com
©by RF Monolithics, Inc.
Bit
15
1
Bit
14
1
where M is M[7..0] of the Wake-up Timer Period Register.
Bit
13
0
Email: info@rfm.com
Bit
12
0
Duty Cycle(%) = ((D[6..0] * 2 )+ 1)/M * 100
Bit
11
1
[POR=C80Eh]
Bit
10
0
Bit
9
0
Bit
8
0
DC6
Bit
7
DC5
Bit
6
DC4
Bit
5
DC3
Bit
4
DC2
Bit
3
DC1
Bit
2
DC0
Bit
TRC101 - 4/8/08
1
Page 30 of 42
DCEN
Bit
0