ATA5749-6DQY Atmel, ATA5749-6DQY Datasheet - Page 16

• Manufacturer Part Number: ATA5749-6DQY
• Description: IC XMITTER PLL FRACT-N 10-TSSOP
• Manufacturer: Atmel

Specifications of ATA5749-6DQY

• Frequency: 300MHz ~ 450MHz
• Applications: General Data Transfer
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 40 kbps
• Power - Output: 12.5dBm
• Current - Transmitting: 8.8mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 1.9 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 10-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -

Figure 6-5.
16
1
2
3
)"register partly programmed": negative SCK
edge of 32-bit register programming MSB-1
(S433_N315)
) "register programmed'" negative SCK
edge of 32-bit register programming LSB
(CLK_ON)
) "PLL locked" 1280 XTO cycles (T
register programmed and XTO_RDY = 'High'
To transition from one state to another, only the
conditions next to the transition arrows must be
fulfilled. No additional settings are required.
Atmel ATA5749
TX_Mode_2
State Diagram of Operating Modes
SDIN_TXDIN = 'High'
(ASK_NFSK = 'High' and
ASK_NFSK = 'High' and
SDIN_TXDIN = 'High')
ASK_NFSK = 'Low' or
SDIN_TXDIN = 'Low'
EN = 'Low'
SDIN_TXDIN = 'Low'
PLL locked
EN = 'Low'
PLL
3
) after
TX_Mode_1
SDIN_TXDIN = 'High'
SDIN_TXDIN = 'Low'
EN = 'Low'
EN = 'Low'
register programmed
XTO_RDY = 'High'
CLK_Only = 'Low'
register programmed
CLK_Only = 'Low'
register parity programmed
register parity programmed
CLK_Only = 'Low'
CLK_Only = 'Low'
SDIN_TXDIN = 'Low'
2
EN = 'High'
2
Configuration_Mode_2
Configuration_Mode_1
Reset_Register_Mode
Start-Up_Mode_1
Start-Up_Mode_2
OFF_Mode
1
1
SDIN_TXDIN = 'Low'
EN = 'High'
SDIN_TXDIN = 'Low'
EN = 'Low'
register programmed
CLK_Only = 'High'
register programmed
CLK_Only = 'High'
XTO_RDY = 'High'
2
2
SDIN_TXDIN = 'High'
Clock_only_Mode
SDIN_TXDIN = 'Low'
EN = 'Low'
EN = 'Low'
9128G–RKE–03/11