RFPIC12F675HT-I/SS Microchip Technology, RFPIC12F675HT-I/SS Datasheet - Page 31
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RFPIC12F675HT-I/SS
Manufacturer Part Number
RFPIC12F675HT-I/SS
Description
IC MCU 1KX14 RF FSK/ASK 20SSOP
Manufacturer
Microchip Technology
Series
PIC®r
Specifications of RFPIC12F675HT-I/SS
Frequency
850MHz ~ 950MHz
Applications
RKE, Security Systems
Modulation Or Protocol
ASK, FSK
Data Rate - Maximum
40 kbps
Power - Output
10dBm
Current - Transmitting
14mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1024 x 14 words Flash, 128 x 8 Byte EEPROM, 64 x 8 Byte SRAM
Voltage - Supply
2V ~ 5.5V
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
1024 B
Data Ram Size
64 B
Interface Type
USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC124002 - MOD SKT PROMATEII 18SOIC/20SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Details
Other names
RFPIC12F675HT-ISS
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
RFPIC12F675HT-I/SS
Manufacturer:
MICROCHIP
Quantity:
12 000
5.1
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock
or run asynchronously.
In Counter and Timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
FIGURE 5-2:
2003 Microchip Technology Inc.
Note:
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
Timer1 Modes of Operation
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
clock.
TIMER1 INCREMENTING EDGE
Preliminary
5.2
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
5.3
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
Note:
Timer1 Interrupt
Timer1 Prescaler
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
rfPIC12F675
DS70091A-page 29