ATA6286N-PNQW Atmel, ATA6286N-PNQW Datasheet - Page 13

• Manufacturer Part Number: ATA6286N-PNQW
• Description: IC CTRL/XMITTER 433MHZ 32-VQFN
• Manufacturer: Atmel

Specifications of ATA6286N-PNQW

• Frequency: 433MHz
• Applications: TPM (Tire Pressure Monitor)
• Modulation Or Protocol: ASK, FSK
• Data Rate - Maximum: 20 kbps
• Power - Output: 6dBm
• Current - Transmitting: 8.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 512 B
• Interface Type: SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 9
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / Rohs Status: Details

4.5.1.2
4.5.2
4.5.2.1
4958BS–AUTO–01/09
Transmission with ENABLE = High
FSK Mode
FSK Mode
The ATA6285N/ATA6286N is activated by FSK = High, ASK = Low. The microcontroller is then
switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically
(i.e., the microcontroller waits until the XTO and CLK are ready. After another time period of
ASK = H. The ATA6285N/ATA6286N is then ready for FSK modulation. The microcontroller
starts to switch on and off the capacitor between the crystal load capacitor and GND by means
of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency
is lower, if FSK = H output frequency is higher. After transmission, FSK stays High and ASK is
switched to Low and the microcontroller returns back to internal clocking. Then, the
ATA6285N/ATA6286N is switched to power-down mode with FSK = Low.
Figure 4-3.
The ATA6285N/ATA6286N is activated by ENABLE = High, FSK = High and ASK = Low. The
microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is acti-
vated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After
another time period of 250 µs, the PLL is locked and ready to transmit. The power amplifier is
switched on with ASK = H. The ATA6285N/ATA6286N is then ready for FSK modulation. The
microcontroller starts to switch on and off the capacitor between the crystal load capacitor and
GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the
output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is
switched to Low and the microcontroller returns back to internal clocking. Then, the
ATA6285N/ATA6286N is switched to power-down mode with ENABLE = Low and FSK = Low.
250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with
ASK
FSK
CLK
Timing FSK Mode with ENABLE Open
Power-down
ATA6285N/ATA6286N [Preliminary]
T
XTO
Power-up,
PA off
> 250 µs
(f
Power-up,
RF
PA on
= High)
(f
Power-up,
RF
PA off
= Low)
Power-down
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