AS3977-BQFT austriamicrosystems, AS3977-BQFT Datasheet - Page 22

• Manufacturer Part Number: AS3977-BQFT
• Description: IC RF TRANSMITTER FSK 16-QFN
• Manufacturer: austriamicrosystems

Specifications of AS3977-BQFT

• Frequency: 300MHz ~ 928MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 100 kbps
• Power - Output: 10dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad, 16-HVQFN, 16-SQFN, 16-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Current - Transmitting: -

AS3977
Data Sheet - A p p l i c a t i o n I n f o r m a t i o n
In any case, the SDI master has to reset the SDI interface on the last bit of the data in order to stop the communication
by applying an Enable LOW pulse (duration: min > 1 SDI CLK cycle, max: < 1/f
Power On Reset
For stable start up of the AS3977 and to avoid unwanted crystal oscillation, it is strongly recommended to perform a
power on reset (Hardware Reset Method). This can be performed as described in
every time when the supply voltage is less than the minimum allowed value
Table 19. Power On Reset
Writing of Data to Addressable Registers
When the Power Down Mode is left, the level of CLK at the rising edge of ENABLE determines the sampling edge of
CLK. If CLK is low, when ENABLE rises, DATAI is sampled at the falling edge of CLK (see
CLK is high when ENABLE rises, DATAI is sampled at the rising edge of CLK.
An Enable LOW pulse indicates the end of the WRITE command after register has been written.
Figure 8
of CLK signal.
Figure 8. Writing of a Single Byte (falling edge sampling)
www.austriamicrosystems.com
ger than 2
In case the ENABLE line has been lon-
ENABLE
DATAIO
CLK
over condition is determined here
illustrates a write command in which the initialization of DATAIO take over condition is done at the falling edge
16
Step
Enable low must be shorter than 2
clock cycles low, data take
1
2
3
the power conditions and the data takeover condition
0
1
A5
A4
16
clock cycles to keep
Power on reset complete after xtal start up + 2
A3
Apply Enable high pulse (Low-High-Low transition)
A2
Revision 3.5
A1
Apply Power to the AS3977
Hardware Reset Method
A0
AS3977 at this
sampled from
Data D7 is
edge
D7
D6
Microcontroller
(see Operating Conditions on page
transferred
Data D4 is
D5
crystal
from
Table 19
D4
* 2
16
D3
16
).
Figure 8
and must be carried out
xtal cycles
D2
ENABLE falling edge
D1
signals end of write
and
Data D7-D0
is moved to
A5-A0 here
Address
Figure
D0
9), if
22 - 45
8).