TXC101 RFM, TXC101 Datasheet - Page 21

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TXC101

Manufacturer Part Number
TXC101
Description
IC TX 300MHZ-1GHZ 16-TSSOP
Manufacturer
RFM
Series
TXr
Datasheet

Specifications of TXC101

Frequency
300MHz ~ 1GHz
Applications
General Data Transfer
Modulation Or Protocol
FSK, OOK
Data Rate - Maximum
512kbps
Power - Output
3dBm
Current - Transmitting
13mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.2 V ~ 5.4 V
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Other names
583-1098-2

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Power Management Register
The Power Management Register enables/disables the following:
Bit [15..8] – Command Code: These bits are the command code that is sent serially to the processor that identifies the bits to be
Bit [7..6] – Transmit Chain Automatic Enable [EEPROM Mode]: These bits enable the entire transmit chain when set. When TX1
Bit [5] – Crystal Oscillator Enable: This bit enables the oscillator circuit when set. The oscillator provides the reference signal for
Bit [4] – Synthesizer Enable: This bit enables the synthesizer when set. The synthesizer contains the PLL, oscillator, and VCO for
NOTE:
synthesizer is started. Directly after activation of the synthesizer, the RF VCO is calibrated to ensure proper operation in the
programmed frequency band. It is suggested that recalibration routines be added to compensate for significant changes in
temperature and supply voltages.
Bit [3] –Power Amplifier Enable: This bit enables the power amplifier when set. The power amplifier may be manually enabled
Bit [2] – Low Battery Detector: This bit enables the battery voltage detect circuit when set. The battery detector can be
Bit [1] – Wake-up Timer Enable: This bit enables the wake-up timer when set. See Wake-up Timer Period Register section for
Bit [0] – Clock Output Disable: This bit disables the oscillator clock output when set. On chip reset or power up, clock output is on
Sleep Mode
The device enters sleep mode by writing a 0xC001 which disables all functions and turns off the clock output. If the clock output is
not disabled by writing a ‘1’ to bit 0, the oscillator circuit will continue to run and draw additional current.
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©by RF Monolithics, Inc.
Bit
15
1
Bit
14
1
the synthesizer when setting the transmit frequency of use.
controlling the channel frequency. This must be enabled when the transmitter is enabled. The oscillator also must be
enabled to provide the reference frequency for the PLL. On power-up the synthesizer performs a calibration automatically.
If there are significant changes in voltage or temperature, recalibration can be performed by simply disabling the synthesizer
and re-enabling it.
For correct operation of the frequency synthesizer, the frequency and band of operation need to be programmed before the
from other functions.
programmed to 32 different threshold levels. See Battery Detect Threshold and Clock Output Register section for
programming.
programming the wake-up timer interval value.
so that a processor may begin execution of any special setup sequences as required by the designer. See Battery Detect
Threshold and Clock Output Register section for programming details.
Transmit Chain
PLL
Power Amplifier
Synthesizer
Crystal Oscillator
Low battery Detect Circuit
Wake-up Timer
Clock Output
is set, the oscillator and synthesizer turn-on are controlled by the chip. When the Data Transmit Command is issued, the
oscillator is enabled. As soon as a stable frequency is reached the synthesizer is enabled. When TX0 is set, this turns on
the power amplifier after the PLL has successfully achieved lock.
written to the Power Management register.
Bit
13
0
Bit
12
0
Email: info@rfm.com
Bit
11
0
Bit
10
0
Manual
PA on after synth locked
Osc and Synth on when Transmit Cmd issued
Osc and Synth on after Transmit Cmd,
then PA on after synth locked
Bit
9
0
Bit
[POR=C000h]
8
0
TX1
Bit
7
Function
TX0
Bit
6
OSCEN
Bit
5
SYNEN
Bit
4
TX1
0
0
1
1
PAEN
TX0
Bit
3
0
1
0
1
LBDEN
Bit
2
WKUPEN
Bit
1
TXC101 - 4/8/08
Page 21 of 27
CLKEN
Bit
0

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