PIC16F1824-I/ML Microchip Technology, PIC16F1824-I/ML Datasheet - Page 244

• Manufacturer Part Number: PIC16F1824-I/ML
• Description: IC PIC MCU 8BIT 14KB FLSH 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1824-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-VQFN Exposed Pad
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16(L)F1824/1828
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDA hold times
Figure 25-2
ule in Master mode.
interface module in Slave mode.
FIGURE 25-2:
DS41419B-page 244
2
C interface supports the following modes and
SDA
SCL
is a block diagram of the I
Figure 25-3
MSSP1 BLOCK DIAGRAM (I
SDA in
is a diagram of the I
Bus Collision
SCL in
2
C interface mod-
Read
MSb
Generate (SSP1CON2)
Address Match detect
Preliminary
Write collision detect
2
end of XMIT/RCV
Start bit, Stop bit,
State counter for
Clock arbitration
C
Start bit detect,
Stop bit detect
Acknowledge
SSP1BUF
SSP1SR
2
C™ MASTER MODE)
LSb
Write
Clock
Shift
data bus
Internal
Set/Reset: S, P, SSP1STAT, WCOL, SSPOV
Reset SEN, PEN (SSP1CON2)
Set SSP1IF, BCL1IF
 2010 Microchip Technology Inc.
[SSPM 3:0]
Baud rate
generator
(SSP1ADD)