PIC16F1828-I/ML Microchip Technology, PIC16F1828-I/ML Datasheet - Page 289

• Manufacturer Part Number: PIC16F1828-I/ML
• Description: IC PIC MCU 8BIT 14KB FLASH 20QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1828-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-VFQFN Exposed Pad
• Controller Family/series: PIC16F
• No. Of I/o's: 18
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 256Byte
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

25.6.13.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 25-38:
FIGURE 25-39:
 2010 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCL1IF
P
SSP1IF
SDA
SCL
PEN
BCL1IF
P
SSP1IF
Bus Collision During a Stop
Condition
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
SDA asserted low
Assert SDA
T
BRG
T
BRG
Preliminary
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSP1ADD and
counts down to 0. After the BRG times out, SDA is
sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’
low before SDA is allowed to float high, a bus collision
occurs. This is another case of another master
attempting to drive a data ‘0’
PIC16(L)F1824/1828
SCL goes low before SDA goes high,
set BCL1IF
T
(Figure
BRG
T
BRG
25-37). If the SCL pin is sampled
(Figure
SDA sampled
low after T
set BCL1IF
‘0’
‘0’
DS41419B-page 289
‘0’
‘0’
25-38).
BRG
,