PIC16F1828-I/SO Microchip Technology, PIC16F1828-I/SO Datasheet - Page 4
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PIC16F1828-I/SO
Manufacturer Part Number
PIC16F1828-I/SO
Description
IC PIC MCU 8BIT 14KB FLSH 20SOIC
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheets
1.PIC16F722-ISS.pdf
(8 pages)
2.PIC16F1826-IP.pdf
(40 pages)
3.PIC16F1824-ISL.pdf
(2 pages)
4.PIC16F1824-ISL.pdf
(419 pages)
5.PIC16F1824-ISL.pdf
(10 pages)
Specifications of PIC16F1828-I/SO
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Controller Family/series
PIC16F
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
32MHz
No. Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F1828-I/SO
Manufacturer:
TI/NSC
Quantity:
101
Part Number:
PIC16F1828-I/SO
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16(L)F1824/1828
EXAMPLE 1:
For other combinations of F
Instruction cycle delay counts, refer to
TABLE 3:
DS80510C-page 4
BSF
BCF
MOVF
Note:
In
required to complete the full conversion. Each T
cycle consists of 8 T
provided to stop the A/D conversion after 86
instruction cycles and terminate the conversion at
the correct time as shown in the figure above.
Affected Silicon Revisions
A1
F
F
F
X
Figure
OSC
OSC
OSC
T
ADCON0, ADGO
ADCON0, ADGO
ADRESH, W
AD
The exact delay time will depend on the
T
counts shown in the timing diagram above
apply to this example only. Refer to
Table 3
other configurations.
/64
/32
/16
A3
AD
1, 88 instruction cycles (T
INSTRUCTION CYCLE DELAY
COUNTS BY T
divisor (ADCS) selection. The T
CODE EXAMPLE OF
INSTRUCTION CYCLE
DELAY
for the required delay counts for
Instruction Cycle Delay
CY
; Start ADC conversion
; Provide 86
; Terminate the
; Read conversion
instruction cycle
delay here
conversion manually
result
periods. A fixed delay is
OSC
AD
Counts
, T
172
86
43
SELECTION
AD
Table
values and
CY
3.
) will be
CY
AD
2. Module: Oscillator
2.1 HS Oscillator
3. Module: Enhanced Capture Compare
3.1 Enhanced PWM
3.2 Enhanced PWM
The HS oscillator requires a minimum voltage of
3.0 volts (at 65°C or less) to operate at 20 MHz.
Work around
None.
Affected Silicon Revisions
When the PWM is configured for Full-Bridge mode
and the duty cycle is set to 0%, writing the
PxM<1:0> bits to change the direction has no
effect on PxA and PxC outputs.
Work around
Increase the duty cycle to a value greater than 0%
before changing directions.
Affected Silicon Revisions
In PWM mode, when the duty cycle is set to 0%
and the STRxSYNC bit is set, writing the STRxA,
STRxB, STRxC and the STRxD bits to enable/
disable steering to port pins has no effect on the
outputs.
Work around
Increase the duty cycle to a value greater than 0%
before enabling/disabling steering to port pins.
Affected Silicon Revisions
A1
A1
A1
X
X
X
A3
A3
A3
PWM (ECCP)
2010 Microchip Technology Inc.