LMP91000SDE/NOPB National Semiconductor, LMP91000SDE/NOPB Datasheet - Page 6

IC AFE INTERFACE 14-LLP

LMP91000SDE/NOPB

Manufacturer Part Number
LMP91000SDE/NOPB
Description
IC AFE INTERFACE 14-LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of LMP91000SDE/NOPB

Number Of Channels
1
Voltage - Supply, Analog
2.7 V ~ 5.25 V
Voltage - Supply, Digital
2.7 V ~ 5.25 V
Package / Case
14-WFDFN Exposed Pad
Input Voltage
5.25V
Supply Current
10µA
Ic Output Type
Analog
Sensor Case Style
QFN
No. Of Pins
14
Supply Voltage Range
2.7V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Number Of Bits
-
Lead Free Status / Rohs Status
Compliant
Other names
LMP91000SDE/NOPBTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LMP91000SDE/NOPB
Manufacturer:
TI/德州仪器
Quantity:
20 000
Part Number:
LMP91000SDE/NOPB
0
www.national.com
Symbol
t
t
t
t
t_timeout
t
t
t
BUF
VD;DAT
VD;ACK
SP
EN;START
EN;STOP
EN;HIGH
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Operating Ratings is not implied. Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such
conditions.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-
Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: All non-power pins of this device are protected against ESD by snapback devices. Voltage at such pins will rise beyond absmax if current is forced into
pin.
Note 4: The maximum power dissipation is a function of T
temperature is P
Note 5: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that T
T
Note 6: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 7: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using statistical quality
control (SQC) method.
Note 8: Offset voltage temperature drift is determined by dividing the change in VOS at the temperature extremes by the total temperature change.
Starting from the measured voltage offset at temperature T1 (V
formula: V
Note 9: At such currents no accuracy of the output voltage can be expected.
Note 10: This parameter includes both A1 and TIA's noise contribution.
Note 11: In case of external reference connected, the noise of the reference has to be added.
Note 12: For negative bias polarity the Internal Zero is set at 67% VREF.
Note 13: LMP91000 provides an internal 300ns minimum hold time to bridge the undefined region of the falling edge of SCL.
Note 14: This parameter is guaranteed by design or characterization.
Timing Diagram
A
. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically.
OS_RW
Parameter
Bus free time between a STOP and START
condition
Data valid time
Data valid acknowledge time
Pulse width of spikes that must be
suppressed by the input
SCL and SDA Timeout
I
I
time between consecutive I
enabling and disabling
2
2
C Interface Enabling
C Interface Disabling
(T2)=V
DMAX
= (T
OS_RW
J
J(MAX)
= T
(T1)+ABS(T2–T1)* TcV
A
. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T
- T
A
)/ θ
JA
All numbers apply for packages soldered directly onto a PC board.
filter(Note
2
C interface
OS_RW
FIGURE 1. I
14)
J(MAX)
.
OS_RW
, θ
JA
, and the ambient temperature, T
Conditions
(T1)), the voltage offset at temperature T2 (V
2
C Interface Timing Diagram
6
A
. The maximum allowable power dissipation at any ambient
OS_RW
Min
600
600
600
4.7
25
(T2)) is calculated according the following
Typ
Max
3.45
3.45
100
50
30132541
Units
ms
µs
µs
µs
ns
ns
ns
ns
J
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