73M1903C-IM/F Maxim Integrated Products, 73M1903C-IM/F Datasheet - Page 14

• Manufacturer Part Number: 73M1903C-IM/F
• Description: IC MODEM AFE MULTIREGIONAL 32QFN
• Manufacturer: Maxim Integrated Products

Specifications of 73M1903C-IM/F

• Number Of Channels: 2
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Number Of Bits: -

73M1903C Data Sheet
Register01 (TEST): Address 01h
Reset State 00h
Bit 7
TMEN
TMEN
DIGLB
ANALB
INTLB
CkoutEn
RXPULL
SPOS
HC
Register06 (REV): Address 06h
Reset State 60h
Rev(3:0)
FSDEn
14
Bit 7
Bit 6
DIGLB
(0X01[7])
0 = Normal operation
1 = Enable test modes.
(0X01[6])
0 = Normal operation
1 = Tie the serial bit stream from the digital transmit filter output to the digital receive filter
(0X01[5])
0 = Normal operation
1 = Tie the analog output of the transmitter to the analog input of the receiver.
(0X01[4])
0 = Normal operation
1 = Tie the digital serial bit stream from the analog receiver output to the analog transmitter
(0X01[3])
1 =
0 =
(0X01[2])
1 =
0 =
(0X01[1])
1 =
0 =
(0X01[0])
1 =
0 =
(0X06[7:4]) Contain the revision ID of the 73M1903C device. The rest of this register is for
chip development purposes only and is not intended for customer use. Do not write to
reserved locations.
(0X06[3])
used.
1 = Delayed frame sync for daisy chaining of additional 73M1903C devices.
0 = FSD tristated, for normal operation.
Bit 6
Rev(3:0)
input.
input.
Enable the CLKOUT output; This bit must be set after the FSDEn bit is set to enable
daisy chain mode.
CLKOUT tri-stated, for normal operation.
Pulls DC Bias to RXAP/RXAN pins, thru 100Kohm each, to VREF, to be used in
testing Rx path.
No DC Bias to RXAP/RXAN pins
Control frames occur after one quarter of the time between data frames has elapsed.
Control frames occur half way between data frames.
Control frame generation is under hardware control, bit 0 of data frames on SDIN is bit
0 of the transmit word and control frames happen automatically after every data frame.
Control frame generation is under software control, bit 0 of data frames on SDIN is a
control frame request bit and control frames happen only on request.
Bit 5
ANALB
Test Mode Enable.
Digital Loop back Enable
Analog Loop back Enable
Internal Loop back Enable. (Remote Analog Loop back)
Clock Output Enable
Delayed Frame Sync Enable. This bit shall be enabled if the daisy chain mode is
Bit 5
Bit 4
INTLB
Bit 4
Bit 3
CkoutEn
FSDEn
Bit 3
Bit 2
RXPULL
Bit 2
Bit 1
SPOS
Reserved
Bit 1
Bit 0
HC
Bit 0
DS_1903C_033
Rev. 5.0