XC3S200-4TQ144I Xilinx Inc, XC3S200-4TQ144I Datasheet - Page 85

no-image

XC3S200-4TQ144I

Manufacturer Part Number
XC3S200-4TQ144I
Description
IC FPGA SPARTAN 3 144TQFP
Manufacturer
Xilinx Inc
Series
Spartan™-3r
Datasheet

Specifications of XC3S200-4TQ144I

Number Of Logic Elements/cells
4320
Number Of Labs/clbs
480
Total Ram Bits
221184
Number Of I /o
97
Number Of Gates
200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-LQFP
Package
144TQFP
Family Name
Spartan®-3
Device Logic Units
4320
Device System Gates
200000
Maximum Internal Frequency
630 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
97
Ram Bits
221184
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC3S200-4TQ144I
Manufacturer:
XILINX
Quantity:
1 600
Part Number:
XC3S200-4TQ144I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S200-4TQ144I
Manufacturer:
XILINX
0
Part Number:
XC3S200-4TQ144I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 55: Block RAM Timing
Clock Distribution Switching Characteristics
Table 56: Clock Distribution Switching Characteristics
DS099-3 (v2.5) December 4, 2009
Product Specification
98
Notes:
1.
2.
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
Hold Times
T
Clock Timing
T
T
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I-input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0- and
I1-inputs. Same as BUFGCE enable CE-input
BCKO
BDCK
BCKD
BPWH
BPWL
The numbers in this table are based on the operating conditions set forth in
For minimums, use the values reported by the Xilinx timing analyzer.
For minimums, use the values reported by the Xilinx timing analyzer.
Symbol
R
When reading from the Block
RAM, the time from the active
transition at the CLK input to
data appearing at the DOUT
output
Time from the setup of data at
the DIN inputs to the active
transition at the CLK input of the
Block RAM
Time from the active transition
at the Block RAM’s CLK input to
the point where data is last held
at the DIN inputs
Block RAM CLK signal High
pulse width
Block RAM CLK signal Low
pulse width
Description
Description
Spartan-3 FPGA Family: DC and Switching Characteristics
www.xilinx.com
0.43
1.19
1.19
Min
0
-
-5
Max
2.09
Table
-
-
Speed Grade
31.
Symbol
T
T
GIO
GSI
0.49
1.37
1.37
Min
0
-
0.36
0.53
-4
Speed Grade
-5
Maximum
Max
2.40
-
-
0.41
0.60
-4
Units
ns
ns
ns
ns
ns
Units
ns
ns
85

Related parts for XC3S200-4TQ144I