XC2V40-5FG256I Xilinx Inc, XC2V40-5FG256I Datasheet - Page 76

• Manufacturer Part Number: XC2V40-5FG256I
• Description: IC FPGA VIRTEX-II 256FGBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-IIr

Specifications of XC2V40-5FG256I

• Number Of Labs/clbs: 64
• Total Ram Bits: 73728
• Number Of I /o: 88
• Number Of Gates: 40000
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Logic Elements/cells: -

.
Table 31: Master/Slave Serial Mode Timing Characteristics
Master/Slave SelectMAP Parameters
Figure 5
Virtex-II Pro Platform FPGA User Guide
DS031-3 (v3.5) November 5, 2007
Product Specification
Notes:
1.
CCLK
If no provision is made in the design to adjust the frequency of CCLK, F
is a generic timing diagram for data loading using SelectMAP. For other data loading diagrams, refer to the
Serial DOUT
R
Serial DOUT
DIN setup/hold, slave mode
DIN setup/hold, master mode
DOUT
High time
Low time
Maximum start-up frequency
Maximum frequency
Frequency tolerance, master mode with
respect to nominal
Serial DIN
Serial DIN
(Output)
CCLK
CCLK
Description
1
Figure 4: Master Serial Mode Timing Sequence
T
1
Figure 3: Slave Serial Mode Timing Sequence
DSCK
(Figure
T
DCC
(Figure
.
3)
T
4)
CKDS
2
2
T
CCD
www.xilinx.com
4
References
T
Virtex-II Platform FPGAs: DC and Switching Characteristics
CCH
Figure
1/2
1/2
3
4
5
CC_SERIAL
should not exceed F
T
F
F
T
3
DSCK
CC_STARTUP
Symbol
CC_SERIAL
DCC
T
T
T
T
CCO
CCO
CCH
CCL
/T
/T
5
CCD
CKDS
T
CCL
CC_STARTUP
5.0/0.0
5.0/0.0
Value
+45%
–30%
12.0
5.0
5.0
50
66
ds083-3_08_111104
ds083-3_09_111104
(1)
.
MHz, max
MHz, max
Module 3 of 4
ns, max
ns, min
ns, min
ns, min
ns, min
Units
28