M058ZAN Nuvoton Technology Corporation of America, M058ZAN Datasheet - Page 177

• Manufacturer Part Number: M058ZAN
• Description: IC MCU 32BIT 32KB FLASH 33QFN
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro M051™r

Specifications of M058ZAN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 5x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 33-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.5.7
6.5.7.1 Master Transmitter Mode
6.5.7.2 Master Receiver Mode
6.5.7.3 Slave Receiver Mode
6.5.7.4 Slave Transmitter Mode
NuMicro M051
The on-chip I2C ports support five operation modes, Master transmitter, Master receiver, Slave
transmitter, Slave receiver, and GC call.
In a given application, I2C port may operate as a master or as a slave. In the slave mode, the I2C
port hardware looks for its own slave address and the general call address. If one of these
addresses is detected, and if the slave is willing to receive or transmit data from/to master(by
setting the AA bit), acknowledge pulse will be transmitted out on the 9th clock, hence an interrupt
is requested on both master and slave devices if interrupt is enabled. When the microcontroller
wishes to become the bus master, the hardware waits until the bus is free before the master
mode is entered so that a possible slave action didn’t be interrupted. If bus arbitration is lost in the
master mode, I2C port switches to the slave mode immediately and can detect its own slave
address in the same serial transfer.
Serial data output through SDA while SCL outputs the serial clock. The first byte transmitted
contains the slave address of the receiving device (7 bits) and the data direction bit. In this case
the data direction bit (R/W) will be logic 0, and it is represented by “W” in the Figure 6.5-11. Thus
the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is
transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate
the beginning and the end of a serial transfer.
In this case the data direction bit (R/W) will be logic 1, and it is represented by “R” in the Figure
6.5-12. Thus the first byte transmitted is SLA+R. Serial data is received via SDA while SCL
outputs the serial clock. Serial data is received 8 bits at a time. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are output to indicate the beginning
and end of a serial transfer.
Serial data and the serial clock are received through SDA and SCL. After each byte is received,
an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning
and end of a serial transfer. Address recognition is performed by hardware after reception of the
slave address and direction bit.
The first byte is received and handled as in the slave receiver mode. However, in this mode, the
direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA
while the serial clock is input through SCL. START and STOP conditions are recognized as the
beginning and end of a serial transfer.
Modes of Operation
™
Series Technical Reference Manual
- 177 -
Publication Release Date: Sept 14, 2010
Revision V1.2