NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 63
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NUC100LC1BN
Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.16 PDMA Controller (PDMA)
5.16.1 Overview
5.16.2 Features
NuMicro™ NUC100 Medium Density contains a peripheral direct memory access (PDMA)
controller that transfers data to and from memory or transfer data to and from APB devices. The
PDMA has nine channels of DMA (Peripheral-to-Memory or Memory-to-Peripheral or Memory-to-
Memory). For each PDMA channel (PDMA CH0~CH8), there is one word buffer as transfer buffer
between the Peripherals APB devices and Memory.
Software can stop the PDMA operation by disable PDMA [PDMACEN]. The CPU can recognize
the completion of a PDMA operation by software polling or when it receives an internal PDMA
interrupt. The PDMA controller can increase source or destination address or fixed them as well.
Notice: NuMicro™ NUC100 Low Density only has 1 PDMA channel (channel 0).
Up to nine DMA channels. Each channel can support a unidirectional transfer (Low
Density only has 1 PDMA channel)
AMBA AHB master/slave interface compatible, for data transfer and register read/write
Support source and destination address increased mode or fixed mode
Hardware channel priority. DMA channel has the highest priority and channel has the
lowest priority
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NuMicro™ NUC100 Data Sheet
Publication Release Date: Nov 11, 2010
Revision V2.00