NUC100LC1BN Nuvoton Technology Corporation of America, NUC100LC1BN Datasheet - Page 453
![IC MCU 32BIT 32KB FLASH 48LQFP](/photos/28/73/287342/nuc100lc1bn_sml.jpg)
NUC100LC1BN
Manufacturer Part Number
NUC100LC1BN
Description
IC MCU 32BIT 32KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™r
Specifications of NUC100LC1BN
Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, LVD, POR, PS2, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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5.14 PS2 Device Controller (PS2D)
5.14.1 Overview
5.14.2 Features
PS/2 device controller provides basic timing control for PS/2 communication. All communication
between the device and the host is managed through the CLK and DATA pins. Unlike PS/2
keyboard or mouse device controller, the received/transmit code needs to be translated as
meaningful code by firmware. The device controller generates the CLK signal after receiving a
request to send, but host has ultimate control over communication. DATA sent from the host to
the device is read on the rising edge and DATA sent from device to the host is change after rising
edge. A 16 bytes FIFO is used to reduce CPU intervention. S/W can select 1 to 16 bytes for a
continuous transmission.
Host communication inhibit and request to send detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
S/W override bus
NuMicro™ NUC100 Series Technical Reference Manual
- 453 -
Publication Release Date: Oct 22, 2010
Revision V1.06
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