ATTINY9-MAH Atmel, ATTINY9-MAH Datasheet - Page 55
![IC MCU AVR 1K FLASH 8UDFN](/photos/12/32/123206/8-udfn-8ma4_sml.jpg)
ATTINY9-MAH
Manufacturer Part Number
ATTINY9-MAH
Description
IC MCU AVR 1K FLASH 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY9-MAH
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-UFDFN Exposed Pad
Core
AVR8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY9-MAHR
Manufacturer:
ST
Quantity:
101
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11.3
11.3.1
11.3.1.1
8127D–AVR–02/10
Clock Sources
Prescaler
Prescaler Reset
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter control Register B (TCCR0B). For details on clock sources and
prescaler, see section “Prescaler”.
The Timer/Counter can be clocked directly by the system clock (by setting the CS2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source.
See
Figure 11-2. Prescaler for Timer/Counter0
Note:
The prescaled clock has a frequency of f
Table 11-6 on page 77
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/CounterCounter, and it is shared by the Timer/Counter Tn. Since the prescaler is not
affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for
situations where a prescaled clock is used. One example of prescaling artifacts occurs when the
timer is enabled and clocked by the prescaler (CS2:0 = 2, 3, 4, or 5). The number of system
PSR10
clk
T0
I/O
Figure 11-2
1. The synchronization logic on the input pins (
Synchronization
for an illustration of the prescaler unit.
CLK_I/O
for details.
). Alternatively, one of four taps from the prescaler can be used as a
Clear
CLK_I/O
/8, f
T0)
CLK_I/O
is shown in
/64, f
CLK_I/O
Figure 11-3 on page
ATtiny4/5/9/10
/256, or f
clk
T0
CLK_I/O
56.
/1024. See
55
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