ATTINY13A-SNR Atmel, ATTINY13A-SNR Datasheet - Page 78
ATTINY13A-SNR
Manufacturer Part Number
ATTINY13A-SNR
Description
IC MCU AVR 1KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY13A-SSH.pdf
(176 pages)
Specifications of ATTINY13A-SNR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
8-SOIC (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
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12.4
12.4.1
78
Register Description.
ATtiny13A
GTCCR – General Timer/Counter Control Register
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 12-2. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal asserted.
This ensures that the Timer/Counter is halted and can be configured without the risk of advanc-
ing during configuration. When the TSM bit is written to zero, the PSR10 bit is cleared by
hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
PSR10
Bit
0x28
Read/Write
Initial Value
clk
T0
I/O
1. The synchronization logic on the input pins (
Synchronization
TSM
R/W
7
0
R
6
–
0
Clear
R
5
–
0
R
4
–
0
T0)
R
is shown in
3
–
0
R
2
–
0
Figure 12-1 on page
clk
R
1
–
0
T0
PSR10
R/W
clk_I/O
0
0
8126E–AVR–07/10
77.
/2.5.
GTCCR
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