ATTINY2313-20MUR Atmel, ATTINY2313-20MUR Datasheet - Page 132
ATTINY2313-20MUR
Manufacturer Part Number
ATTINY2313-20MUR
Description
IC MCU AVR 2K FLASH 20WQFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313-20MUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-WFQFN, Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
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USART Control and
Status Register C –
UCSRC
132
ATtiny2313
• Bit 6 – UMSEL: USART Mode Select
This bit selects between asynchronous and synchronous mode of operation.
Table 51. UMSEL Bit Settings
• Bit 5:4 – UPM1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting.
If a mismatch is detected, the UPE Flag in UCSRA will be set.
Table 52. UPM Bits Settings
• Bit 3 – USBS: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 53. USBS Bit Settings
• Bit 2:1 – UCSZ1:0: Character Size
The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Char-
acter SiZe) in a frame the Receiver and Transmitter use. See
Bit
Read/Write
Initial Value
UPM1
UMSEL
0
0
1
1
0
1
USBS
R
7
–
0
0
1
UMSEL
R/W
6
0
UPM0
Asynchronous Operation
Synchronous Operation
Mode
0
1
0
1
UPM1
R/W
5
0
Stop Bit(s)
1-bit
2-bit
UPM0
R/W
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
0
4
USBS
R/W
3
0
UCSZ1
R/W
2
1
Table 54 on page
UCSZ0
R/W
1
1
UCPOL
R/W
0
0
UCSRC
133.
2543L–AVR–08/10
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