ATTINY26L-8SUR Atmel, ATTINY26L-8SUR Datasheet - Page 103
ATTINY26L-8SUR
Manufacturer Part Number
ATTINY26L-8SUR
Description
IC MCU AVR 2K 5V 8MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY26L-8SUR
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (0.300", 7.50mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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ADC Control and
Status Register –
ADCSR
1477K–AVR–08/10
• Bit 7 – ADEN: ADC Enable
Writing a logical “1” to this bit enables the ADC. By clearing this bit to zero, the ADC is turned off.
Turning the ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, a logical “1” must be written to this bit to start each conversion. In
Free Running mode, a logical “1” must be written to this bit to start the first conversion. The first
time ADSC has been written after the ADC has been enabled, or if ADSC is written at the same
time as the ADC is enabled, a dummy conversion will precede the initiated conversion. This
dummy conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. When a dummy conversion precedes a real conversion, ADSC will stay high
until the real conversion completes. Writing a 0 to this bit has no effect.
• Bit 5 – ADFR: ADC Free Running Select
When this bit is set (one) the ADC operates in Free Running mode. In this mode, the ADC sam-
ples and updates the Data Registers continuously. Clearing this bit (zero) will terminate Free
Running mode.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion completes and the data registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set
(one). ADIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a read-
modify-write on ADCSR, a pending interrupt can be disabled. This also applies if the SBI and
CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete Inter-
rupt is activated.
Bit
$06 ($26)
Read/Write
Initial Value
ADEN
R/W
7
0
ADSC
R/W
6
0
ADFR
R/W
5
0
ADIF
R/W
4
0
ADIE
R/W
3
0
ADPS2
R/W
2
0
ADPS1
R/W
1
0
ADPS0
R/W
0
0
ADCSR
103
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