ATMEGA48PA-PN Atmel, ATMEGA48PA-PN Datasheet - Page 310
ATMEGA48PA-PN
Manufacturer Part Number
ATMEGA48PA-PN
Description
MCU AVR 4KB FLASH 20MHZ 28PDIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA48PA-AN.pdf
(448 pages)
Specifications of ATMEGA48PA-PN
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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27.8.3
Table 27-19. Serial Programming Instruction Set (Hexadecimal values)
8161D–AVR–10/09
Instruction/Operation
Programming Enable
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
Load Instructions
Load Extended Address byte
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
Read Signature Byte
Read Fuse bits
Read Fuse High bits
Read Extended Fuse Bits
Read Calibration Byte
Serial Programming Instruction set
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 27-18. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
Table 27-19 on page 310
(1)
Symbol
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
not used, the used must wait at least t
27-18). In a chip erased device, no 0xFF in the data file(s) need to be programmed.
tent at the selected address at serial output MISO.
operation.
Set RESET to “1”.
Turn V
CC
power off.
Byte 1
$AC
$AC
$4D
$C1
$A0
$F0
$48
$40
$28
$20
$58
$30
$50
$58
$50
$38
and
Figure 27-8 on page 312
ATmega48PA/88PA/168PA/328P
0000 00aa
WD_EEPROM
adr MSB
adr MSB
Byte 2
$53
$80
$00
$00
$00
$00
$00
$00
$00
$00
$08
$08
$00
Instruction Format
before issuing the next byte (See
describes the Instruction set.
Extended adr
0000 000aa
0000 000aa
aaaa aaaa
Minimum Wait Delay
adr LSB
adr LSB
adr LSB
adr LSB
Byte 3
$00
$00
$00
$00
$00
$00
$00
$00
4.5 ms
3.6 ms
9.0 ms
high data byte out
low data byte out
high data byte in
low data byte in
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte in
Byte4
$00
$00
$00
Table
310
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