EFM32G200F64 Energy Micro, EFM32G200F64 Datasheet - Page 140

• Manufacturer Part Number: EFM32G200F64
• Description: MCU 32BIT 64KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F64

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.5.4 EBI_WRTIMING - Write Timing Register
14.5.5 EBI_POLARITY - Polarity Register
31:18
17:16
15:12
11:8
7:2
1:0
31:5
4
3
2
Offset
0x00C
Reset
Access
Name
Bit
Offset
0x010
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
WRHOLD
Sets the number of cycles CSn is held active after the WEn is deasserted.
Reserved
WRSTRB
Sets the number of cycles the WEn is held active. If set to 0, 1 cycle is inserted by HW.
Reserved
WRSETUP
Sets the number of cycles the address setup before WEn is asserted.
Reserved
ARDYPOL
Sets the polarity of the EBI_ARDY line.
ALEPOL
Sets the polarity of the EBI_ALE line.
WEPOL
Sets the polarity of the EBI_WEn line.
Name
Name
Value
0
1
Value
0
1
Mode
ACTIVELOW
ACTIVEHIGH
Mode
ACTIVELOW
ACTIVEHIGH
0x1
0x0
0x0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
RW
RW
RW
RW
RW
Access
Access
Description
ARDY is active low.
ARDY is active high.
Description
ALE is active low.
ALE is active high.
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140
Bit Position
Bit Position
Write Hold Time
Write Strobe Time
Write Setup Time
ARDY Polarity
Address Latch Polarity
Write Enable Polarity
Description
Description
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