MCF51JE256CLL Freescale Semiconductor, MCF51JE256CLL Datasheet - Page 40

• Manufacturer Part Number: MCF51JE256CLL
• Description: IC MCU 32BIT 256K FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51JEr

Specifications of MCF51JE256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, SCI, SPI, USB OTG
• Peripherals: LVD, PWM, WDT
• Number Of I /o: 65
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51JE
• Core: ColdFire V1
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Package: 100LQFP
• Device Core: ColdFire
• Family Name: MCF51JE
• Maximum Speed: 50.33 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 65
• Interface Type: I2C/SCI/SPI
• On-chip Adc: 8-chx12-bit
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Preliminary Electrical Characteristics
3.13
Table 22
1-4
1
2
3
4
No.
Numbers in this column identify elements in
All timing is shown with respect to 20% V
rate control disabled and high drive strength enabled for SPI output pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
12
13
1
2
3
4
5
6
7
8
9
and
SPI Characteristics
1
SPSCK period
Slave MISO disable time
Operating frequency
Enable lead time
Enable lag time
Clock (SPSCK) high or low time
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time
Fall time
Figure 15
Characteristic
through
3
Figure 18
4
2
Preliminary — Subject to Change
DD
Figure 15
and 70% V
Master
Master
Master
Master
Master
Master
Master
Master
Master
Output
Output
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Input
Input
describe the timing requirements for the SPI system.
Table 22. SPI Timing
through
DD
t
Symbol
, unless noted; 100 pF load on all SPI pins. All timing assumes slew
WSPSCK
t
SPSCK
t
t
Lead
t
t
t
t
t
t
f
Lag
t
t
t
HO
RO
t
SU
SU
dis
FO
op
t
t
HI
HI
RI
FI
a
v
Figure
18.
f
t
t
Bus
cyc
cyc
Min
1/2
1/2
15
15
25
—
—
—
—
—
—
—
—
/2048
0
2
4
1
1
0
0
0
– 30
– 30
1024 t
t
t
cyc
cyc
f
f
2048
Max
Bus
Bus
25
25
25
25
—
—
—
—
—
—
—
—
—
—
—
—
1
1
– 25
– 25
/2
/4
cyc
Freescale Semiconductor
t
t
SPSCK
SPSCK
Unit
t
t
t
t
t
t
Hz
Hz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
C
D
D
D
D
D
D
D
D
D
D
D
D
D