NCP1092DG ON Semiconductor, NCP1092DG Datasheet - Page 8

• Manufacturer Part Number: NCP1092DG
• Description: IC INTERFACE CTLR POE-PD 8-SOIC
• Manufacturer: ON Semiconductor
• Series: HIPO™r

Specifications of NCP1092DG

• Controller Type: PoE-PD Interface
• Interface: IEEE 802.3af
• Current - Supply: 500mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Output Voltage: 9.8 V
• Output Current: 500 mA
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Number Of Outputs: 8
• Input Voltage: 57V
• Supply Current: 500mA
• Digital Ic Case Style: SOIC
• No. Of Pins: 8
• Svhc: No SVHC (20-Jun-2011)
• Base Number: 1092
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: NCP1092DGOS

Example for a Targeted Uvlo_on of 35 V:
144 kΩ made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of
140 kΩ (closest values from E96 series). Note that there is
a pull down current of 2.5 mA typ on the UVLO. Assuming
the previous example, this pull down current will create a
(non critical) systematic offset of 350 mV on the Uvlon_on
level of 35 V.
15 percent typical.
Inrush and Operational Current Limitations
an external Rinrush resistor connected between INRUSH
and VPORTN. The low inrush current limit allows smooth
charge of large dc−dc converter input capacitor by limiting
the power dissipation over the internal pass switch. In power
mode, the operational current limit protects the pass switch
indicator stays active as long as RTN voltage stays below the
vds_pgood_off threshold (10 V typical) and the input supply
stay above the Vulvo_off level. Therefore, fast and large
voltage step lower than 10 V are tolerated on the input
without interruption of the converter controller. Higher
input transient will not affect the behavior if RTN does not
exceed 10 V for more than 100 mS. Such input voltage steps
may be introduced by a PSE which is switched to a higher
power supply. In case RTN is still above 10 V after this delay,
the power good is turned off and the pass switch current limit
falls back to the inrush level.
Let’s start with a Rdet of 30.1 kΩ. This gives a Ruvlo of
The external UVLO hysteresis on the NCP1091 is about
Both inrush and operational current limit are defined by
The operational current limit and the power good
Operational current limit
1 V / 10 V
VPORTNx
Figure 7. Inrush and Operational Current Limitation Selection Mechanism
Vds_pgood comparator
Inrush current limit
RTN
VDDA1
0
1
100 mS
Delay
&
detector
http://onsemi.com
Vgs_pgood comparator
Pgood_on
Sense Resistor
8
VDDA1
and the PD application against excessive transient current
and failure on the dc−dc converter output.
charge of Cpd capacitor starts with a current limitation set to
to the INRUSH level. When this capacitor is fully charged,
the current limit switches without any spikes from the inrush
current to the operational current level and the power good
indicator on PGOOD pin is turned on. The capacitor is
considered to be fully charged once the following conditions
are satisfied:
This mechanism is depicted in the following Figure 7.
PGOOD Indicator
circuitry indicating the end of the dc−dc converter input
capacitor charge, and the enabling of the operational current
limit. This indicator is implemented on the PGOOD pin
which goes in open drain state when active and which is
pulled to ground during turn off.
Figure 8. During the inrush phase, the converter controller
is forced in standby mode due to the PGOOD pin forcing low
the under voltage lock out pin of the controller. Once the Cpd
capacitor is fully charged, PGOOD goes in open drain state,
allowing the start up sequence of the converter controller.
Once the input supply reached the Vulvo_on level, the
The NCP1090/91/92 integrate a Power Good indicator
A possible usage of this PGOOD pin is illustrated in
1. The drain−source voltage of the Pass Switch has
2. The gate−source voltage of the Pass Switch is
2 V
decreased below the Vds_pgood_on level (typical
1 V)
sufficiently high (above 2 V typical) which means
the current in the pass switch has decreased below
the current limit.
Pgood_on
Pass Switch
PGOOD
RTN