73S8024RN-32IM/F Maxim Integrated Products, 73S8024RN-32IM/F Datasheet
73S8024RN-32IM/F
Specifications of 73S8024RN-32IM/F
Related parts for 73S8024RN-32IM/F
73S8024RN-32IM/F Summary of contents
Page 1
... DESCRIPTION The Teridian 73S8024RN is a single smart card (ICC) interface IC that can be controlled by a dedicated control bus. The 73S8024RN has been designed to provide full electrical compliance with ISO-7816-3, EMV 4.0 (EMV2000) and NDS specifications. Interfacing with the system controller is done through a ...
Page 2
... FAULT LOGIC ISO-7816 SEQUENCER CLOCK TEMP FAULT ICC I/O BUFFERS Pin numbers reference the 28SO package. [Pin numbers] reference the 32QFN package. {Pin numbers} reference the 20QFN package. Figure 1: 73S8024RN Block Diagram DS_8024RN_020 VPC 6 [3] { [1] {1} GND LDO REGULATOR 14 [12] {6} & ...
Page 3
... Mechanical Drawing (20QFN) ...................................................................................................... 21 14 Package Pin Designation (20QFN) .............................................................................................. 22 15 Mechanical Drawing (32QFN) ...................................................................................................... 23 16 Package Pin Designation (32QFN) .............................................................................................. 24 17 Mechanical Drawing (SO)............................................................................................................. 25 18 Package Pin Designation (SO)..................................................................................................... 25 19 Ordering Information ................................................................................................................... 26 20 Related Documentation ............................................................................................................... 26 21 Contact Information ..................................................................................................................... 26 Revision History ................................................................................................................................... 27 Rev. 1.9 Table of Contents 73S8024RN Data Sheet 3 ...
Page 4
... Figure 4: Deactivation Sequence ............................................................................................................12 Figure 5: Timing Diagram – Management of the Interrupt Line OFF ........................................................13 Figure 6: I/O and I/OUC State Diagram ..................................................................................................14 Figure 7: I/O – I/OUC Delays Timing Diagram ........................................................................................14 Figure 8: 73S8024RN – Typical Application Schematic ...........................................................................15 Figure 9: 20QFN Mechanical Drawing ....................................................................................................21 Figure 10: 20QFN Pin Out ......................................................................................................................22 Figure 11: 32QFN Mechanical Drawing ..................................................................................................23 Figure 12: 32QFN Pin Out ...
Page 5
... DDF card). Must be left open if unused Non-connected pin. 16, 25, 32 Pin Description 32QFN 20 System interface supply voltage and supply voltage for internal circuitry. 3 LDO regulator power supply source. 1 LDO Regulator ground. 21 Digital ground. 73S8024RN Data Sheet when not used, but ...
Page 6
... Data Sheet MICROCONTROLLER INTERFACE Name Pin Pin 28SO 20QFN CMDVCC 19 10 5V/# CLKSTOP 7 – CLKLVL 8 – CLKDIV1 1 18 CLKDIV2 2 19 OFF 23 14 RSTIN 20 11 I/OUC 26 17 AUX1UC 27 – AUX2UC 28 – 6 Pin Description 32QFN 18 Command VCC (negative assertion): Logic low on this pin ...
Page 7
... No card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence. Rev. 1.9 73S8024RN Data Sheet 7 ...
Page 8
... Data Sheet 3 Power Supply and Voltage Supervision The 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. V range to interface with the system controller ...
Page 9
... On-Chip Oscillator and Card Clock The 73S8024RN device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. ...
Page 10
... Data Sheet 7 Activation Sequence The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the . No activation is allowed at this time. The CMDVCC (edge triggered) must then application of V > DDF be set low to activate the card. In order to initiate activation, the card must be present; there can be no ...
Page 11
... Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low Rev. 1 the card is shut down turn I/O (AUX1, AUX2) to reception mode. ), after I reception mode RSTIN may be set high before 73S8024RN Data Sheet at the end normal operation however the sequencer will ...
Page 12
... Data Sheet 8 Deactivation Sequence Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, V and card extraction during the session noted that V fault is generated when V goes lower than V PC The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: • ...
Page 13
... I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 7. Rev. 1.9 OFF is low by card extracted within card session Activation Sequence 73S8024RN Data Sheet OFF is low by any fault within card session section for more 13 ...
Page 14
... Data Sheet Figure 6: I/O and I/OUC State Diagram I/O I/OUC Delay from I/O to I/OUC: Delay from I/OUC to I/O: Figure 7: I/O – I/OUC Delays Timing Diagram 14 Neutral State No I/O reception Yes I/O & not I/OUC No Yes I/OUC No & not I/O Yes ...
Page 15
... GND CLK 73S8024RN SO28 R2 Card detection 20K switch is normally closed CLK track should be routed far from RST, I/O, C4 and C8. Smart Card Connector Figure 8: 73S8024RN – Typical Application Schematic 73S8024RN Data Sheet AUX2UC_to/from_uC AUX1UC_to.from_uC See NOTE 5 I/OUC_to/from_uC See NOTE 3 External_clock_from uC VDD - Rext2 Y1 ...
Page 16
... Data Sheet 12 Electrical Specification 12.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to V Parameter Supply Voltage V Supply Voltage V Input Voltage for Digital Inputs ...
Page 17
... 1.0µ NDS applications C should be ceramic with low F ESR (<100mΩ). NDS applications C should be ceramic with low ESR F (<100mΩ). 73S8024RN Data Sheet Min Typ Max Unit < 5.5v -0.1 0.1 -0.1 0.4 4.60 5.25 4.75 5.25 4.55 5.25 2.80 3 ...
Page 18
... Data Sheet Symbol Parameter Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC and V requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. SHORTL SHORTH INACT Output level, high (I/O, AUX1 AUX2) Output level, high (I/OUC AUX1UC, AUX2UC) ...
Page 19
... C =35Pf ≤ F 20MHz CLK Condition Min -0.3 0 2mA -1mA GND < V < -0.3 0 GND < V < < δ 45% < < 55% CLK 73S8024RN Data Sheet Typ Max Unit 0.3 V 0 V/ns V/ 100 Typ Max Unit kΩ μ +0.3 ...
Page 20
... Data Sheet 12.6 DC Characteristics Symbol Parameter I Supply Current DD I Supply Current PC V supply current when PC I PCOFF 12.7 Voltage / Temperature Fault Detection Circuits Symbol Parameter V fault Voltage supervisor DDF DD threshold) V fault Voltage supervisor PCF PC threshold) V fault Voltage supervisor CCF CC threshold) ...
Page 21
... Rev. 1.9 2.0 4.0 2.0 0.18 / 0.30 2.50 / 2.70 1. 0.50 BOTTOM VIEW Figure 9: 20QFN Mechanical Drawing 73S8024RN Data Sheet 0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 0.20 REF SEATING PLANE SIDE VIEW 0.20 MIN 2.50 / 2.70 K 1.25 / 1.35 0.20 MIN ...
Page 22
... Data Sheet 14 Package Pin Designation (20QFN) 22 CAUTION: Use handling procedures necessary GND 1 VPC 2 TERIDIAN PRES 3 8024RN 4 PRES 5 I/O Figure 10: 20QFN Pin Out DS_8024RN_020 for a static sensitive component 15 XTALIN OFF 14 13 GND 12 VDD 11 RSTIN Rev. 1.9 ...
Page 23
... DS_8024RN_020 15 Mechanical Drawing (32QFN TOP VIEW 0.2 MIN. 0.35 / 0.45 Figure 11: 32QFN Mechanical Drawing Rev. 1.9 73S8024RN Data Sheet / 0.85 NOM. 0.9MAX. SIDE VIEW 3.0 / 3.2 CHAMFERED 0.18 / 0.3 1 0.25 0.5 BOTTOM VIEW 0.00 / 0.005 0.20 REF. SEATING PLANE ...
Page 24
... Data Sheet 16 Package Pin Designation (32QFN) GND VPC 3 CLKSTOP 4 CLKLVL 5 PRES 6 PRES 7 I CAUTION: Use handling procedures necessary TERIDIAN S8024RN Figure 12: 32QFN Pin Out DS_8024RN_020 for a static sensitive component 24 XTALOUT 23 XTALIN OFF 22 GND 21 20 VDD 19 RSTIN CMDVCC 18 17 VDDF_ADJ Rev. 1.9 ...
Page 25
... View I Figure 14: 28SO 73S8024RN Pin Out 73S8024RN Data Sheet .420 (10.668) .390 (9.906) .335 (8.509) .320 (8.128) CAUTION: Use handling procedures necessary for a static sensitive component AUX2UC AUX1UC I/OUC XTALOUT XTALIN OFF GND VDD RSTIN CMDVCC VDDF_ADJ VCC RST CLK 25 ...
Page 26
... Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices http://www.teridian.com. 26 DS_8024RN_020 Order No. Packaging Mark 73S8024RN-IL/F 73S8024RN-IL 73S8024RN-ILR/F 73S8024RN-IL 73S8024RN-32IM/F S8024RN 73S8024RN-32IMR/F S8024RN 73S8024RN-20IM/F 8024RN 73S8024RN-20IMR/F 8024RN Rev. 1.9 ...
Page 27
... Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com Rev. 1.9 1, modified the device block diagram to make pin connect. 9, changed the mechanical drawing for the 20QFN package. page 1 and assigned document number. 73S8024RN Data Sheet 27 ...