WJLXT971ALE.A4-857343 Cortina Systems Inc, WJLXT971ALE.A4-857343 Datasheet - Page 29

• Manufacturer Part Number: WJLXT971ALE.A4-857343
• Description: TXRX ETH 10/100 SGL PORT 64-LQFP
• Manufacturer: Cortina Systems Inc

Specifications of WJLXT971ALE.A4-857343

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 1008-1041

LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Figure 6
5.2.3.1.4
5.2.3.2
5.3
5.3.1
Cortina Systems
MII Interrupt Logic
MII Status Change Register
MII status change is indicated in Register 19 by any of the following four conditions:
Hardware Control Interface
The LXT971A PHY provides a Hardware Control Interface for applications where the
MDIO is not desired. The Hardware Control Interface uses the hardware configuration
pins to set device configuration.
Settings, on page 33.
Operating Requirements
Power Requirements
The LXT971A PHY requires three power supply inputs:
®
• Register 18 provides interrupt enable and mask functions. Setting register bit 18.1 = 1
• Register 19 provides the interrupt status.
• Auto-negotiation complete
• Speed status change
• Duplex status change
• Link status change
• VCCA
• VCCD
LXT971A Single-Port 10/100 Mbps PHY Transceiver
Even X Status Reg
Even X Mask Reg
enables the device to request interrupt via the MDINT_L pin. An active Low on this pin
indicates a status change on the LXT971A PHY. Interrupts may be caused by any of
the following four conditions:
— Auto-negotiation complete
— Speed status change
— Duplex status change
— Link status change
Force Interrupt
For details, see Section 5.4.4, Hardware Configuration
AND
OR
Interrupt Enable
NAND
5.3 Operating Requirements
Interrupt Pin
MDINT_L
B3474-01
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