ELLXT971ABE.A4-870479 Cortina Systems Inc, ELLXT971ABE.A4-870479 Datasheet - Page 21
ELLXT971ABE.A4-870479
Manufacturer Part Number
ELLXT971ABE.A4-870479
Description
TXRX FAST ETH EXT TEMP 64-PBGA
Manufacturer
Cortina Systems Inc
Specifications of ELLXT971ABE.A4-870479
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
1008-1004
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LXT971A PHY
Datasheet
249414, Revision 5.2
13 September 2007
Table 9
Cortina Systems
Configuration and LED Driver Signal Descriptions (Sheet 2 of 2)
®
LXT971A Single-Port 10/100 Mbps PHY Transceiver
PBGA
Pin#
D1
D2
C2
H1
H8
H7
E8
B1
C1
E6
F7
F8
LQFP
Pin#
17
33
32
39
38
37
36
5
6
4
1
2
REFCLK/XI
LED/CFG1
LED/CFG2
LED/CFG3
PWRDWN
TxSLEW0
TxSLEW1
RESET_L
Symbol
PAUSE
SLEEP
RBIAS
XO
Type
I and
I/O
AI
O
I
I
I
I
I
Tx Output Slew Controls 0 and 1.
These pins select the TX output slew rate (rise and fall time)
as follows:
Reset.
This active Low input is ORed with the control register Reset
bit (register bit 0.15). The PHY reset cycle is extended to 258
μs (nominal) after reset is de-asserted.
Reference Current Bias.
This pin provides bias current for the internal circuitry. Must
be tied to ground through a 22.1 kΩ, 1% resistor.
Pause.
When set High, the PHY advertises Pause capabilities during
auto-negotiation.
Sleep.
When set High, this pin enables the PHY to go into a low-
power sleep mode. The value of this pin can be overridden by
register bit 16.6 when in managed mode.
Power Down.
When set High, this pin puts the PHY in a power-down mode.
Reference Clock Input / Crystal Input and Crystal Output.
A 25 MHz crystal oscillator circuit can be connected across XI
and XO. A clock can also be used at XI.
For clock requirements, see
Requirements, on page 30
section.
LED Drivers 1-3.
These pins drive LED indicators. Each LED can display one
of several available status conditions as selected by the LED
Configuration Register. (For details, see
Configuration Register - Address 20, Hex 14, on page
Configuration Inputs 1-3.
These pins also provide initial configuration settings. (For
details, see
page
TxSLEW1
33.)
0
0
1
1
Table 13, Hardware Configuration Settings, on
TxSLEW0
Signal Description
0
1
0
1
in the Functional Description
Section 5.3.2, Clock
Slew Rate (Rise and Fall Time)
4.0 Signal Descriptions
Table 60, LED
3.0 ns
3.4 ns
3.9 ns
4.4 ns
Page 21
91.)