A5191HRTLG-XTD ON Semiconductor, A5191HRTLG-XTD Datasheet - Page 10

• Manufacturer Part Number: A5191HRTLG-XTD
• Description: MODEM HART SGL CMOS 32-LQFP
• Manufacturer: ON Semiconductor

Specifications of A5191HRTLG-XTD

• Data Format: HART
• Interface: CMOS
• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Logic Type: CMOS Modem
• Logic Family: A5191HRT
• Input Level: CMOS
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• Maximum Operating Temperature: + 85 C
• Function: Use in highway addressable remote transducer (HART) field instruments and masters
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 3V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 32
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• No. Of I/o's: 1
• Rohs Compliant: Yes
• Communication Function: HART Modem
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 766-1011

Internal Oscillator Option
crystal or ceramic resonator. A parallel resonant ceramic
resonator can be connected between XIN and XOUT.
Figure 12 illustrates the crystal option for clock generation
using a 460.8 kHz (±1 % tolerance) parallel resonant crystal
and two tuning capacitors Cx. The actual values of the
capacitors may depend on the recommendations of the
manufacturer of the resonator. Typically, capacitors in the
range of 100 pF to 470 pF are used.
External Clock Option
shown in Figure 13 rather than the internal oscillator. In
addition, the A5191HRT consumes less current when an
external clock is used. Minimum current consumption
occurs with the clock connected to XOUT and XIN
connected to V
The oscillator cell will function with either a 460.8 kHz
It may be desirable to use an external 460.8 kHz clock as
XOUT
C
X
Figure 12. Crystal Oscillator
Oscillator
SS
460.8 kHz
Crystal
.
XIN
C
X
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10
Power On Reset
the voltage level on V
= 2.5 V to guarantee correct operation of the digital circuitry.
As illustrated in Figure 14 RESETB should be kept low for
at least t
During start-up the RESETB pin should be kept low until
V
RESET pin
DDH
460.8 kHz
= 2.5 V
Figure 13. Oscillator with External Clock
VDD
POR
Figure 14. Power On Reset Timing
= 10 ns after this threshold level is reached.
XOUT
DD
is above the minimum level V
Oscillator
Crystal
t
POR
= 10 ns
XIN
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PC20101013.2
t
DDH