DS92LX1622SQX/NOPB National Semiconductor, DS92LX1622SQX/NOPB Datasheet - Page 11

• Manufacturer Part Number: DS92LX1622SQX/NOPB
• Description: IC SER/DESER 40LLP
• Manufacturer: National Semiconductor

Specifications of DS92LX1622SQX/NOPB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

t
t
λ
δ
δ
t
t
t
t
t
t
t
t
t
t
t
t
t
t
fdev
fmod
JINR
JINT
RCP
PDC
CLH
CHL
CLH
CHL
ROS
ROH
DD
DDLT
RJIT
RDJ
DPJ
DCCJ
Symbol
STXBW
STX
STXf
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Receiver Output Clock Period
PCLK Duty Cycle
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
LVCMOS Low-to-High Transition
Time
LVCMOS High-to-Low Transition
Time
ROUT Setup Data to PCLK
ROUT Hold Data to PCLK
Deserializer Delay
Deserializer Data Lock Time
Receiver Input Jitter Tolerance
Receiver Clock Jitter
Deserializer Period Jitter
Deserializer Cycle-to-Cycle Clock
Jitter
Spread Spectrum Clocking
Deviation Frequency
Spread Spectrum Clocking
Modulation Frequency
Serializer Output Random
Jitter
Peak-to-peak Serializer
Output Jitter
Serializer Jitter Transfer
Function -3 dB Bandwidth
Serializer Jitter Transfer
Function
Serializer Jitter Transfer
Function Peaking
Frequency
Parameter
Parameter
Serializer output intrinsic random jitter
(cycle-cycle). Alternating – 1,0
pattern.
Serializer output peak-to-peak jitter
includes deterministic jitter, random
jitter, and jitter transfer from serializer
input. Measure with PRBS-7 test
pattern.
PCLK = 50 MHz
Default Registers
PCLK = 50 MHz
Default Registers
PCLK = 50 MHz
Default Registers
t
Default Registers
SSCG[3:0] = OFF
V
3.0V to 3.6V, C
(lumped load)
Default Registers
(
V
3.0V to 3.6V, C
(lumped load)
Default Registers
( )
V
3.0V to 3.6V, CL = 8pF
(lumped load)
Default Registers
( )
Default Registers
Register 0x03h b[0]
(RRFB = 1)
PCLK
SSCG[3:0] = OFF
PCLK
SSCG[3:0] = OFF
PCLK
SSCG[3:0] = OFF
LVCMOS Output Bus
(Figure
RCP
(Note
DDIO
DDIO
DDIO
(Note
= t
: 1.71V to 1.89V or
: 1.71V to 1.89V or
: 1.71V to 1.89V or
Conditions
TCP
10))
17)
9)
Conditions
L
L
= 8 pF
= 8 pF
11
PCLK
PCLK
PCLK
Deserializer Data
Outputs
Deserializer Data
Outputs
10 MHz-50 MHz
10 MHz-50 MHz
50 MHz
10 MHz
50 MHz
10 MHz
50 MHz
10 MHz
50 MHz
20 MHz-50 MHz
20 MHz-50 MHz
Pin/Freq.
Min
4.571T +
0.38T
0.38T
Min
1.3
1.3
1.6
1.6
20
45
8
0.396
0.944
0.04
Typ
500
1.9
±9 kHz to
4.571T +
±0.5% to
±66 kHz
±2.0%
0.5T
0.5T
0.53
Typ
300
120
425
320
320
300
2.0
2.0
2.4
2.4
50
12
T
Max
4.571T
Max
+ 16
100
550
250
600
480
500
500
2.8
2.8
3.3
3.3
55
10
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Units
MHz
kHz
dB
UI
UI
Units
kHz
ms
ns
ns
ns
ns
ns
ps
ps
ps
UI
%
%