DS90UB901QSQX/NOPB National Semiconductor, DS90UB901QSQX/NOPB Datasheet - Page 6

• Manufacturer Part Number: DS90UB901QSQX/NOPB
• Description: IC SER/DESER 10-43MHZ 16B 32LLP
• Manufacturer: National Semiconductor

Specifications of DS90UB901QSQX/NOPB

• Function: Serializer
• Data Rate: 688Mbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 1
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V, 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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LVCMOS PARALLEL INTERFACE
ROUT[13:0]
HSYNC
VSYNC
PCLK
GENERAL PURPOSE INPUT OUTPUT (GPIO)
ROUT[3:0] /
GPIO[5:2]
GPIO[1:0]
BIDIRECTIONAL CONTROL BUS - I
SCL
SDA
MODE
ID[x]
CONTROL AND CONFIGURATION
PDB
LOCK
PASS
RES
BIST MODE
BISTEN
DS90UB902Q Deserializer Pin Descriptions
Pin Name
14, 15, 17, 18,
19, 20, 21, 22,
21, 22, 23, 24
9, 10, 11, 12,
32, 33, 39
Pin No.
23, 24
26, 27
40
29
28
31
37
7
6
5
3
2
1
Input, LVCMOS
Input, LVCMOS
Input, LVCMOS
Input/Output,
Input/Output,
Input/Output,
Input/Output,
Input, analog
w/ pull down
w/ pull down
Open Drain
Open Drain
I/O, Type
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
w/ pull up
LVCMOS
LVCOMS
Outputs,
2
Output,
Output,
Output,
Output,
Output,
C COMPATIBLE
-
Parallel data outputs.
Horizontal SYNC Output
Vertical SYNC Output
Pixel Clock Output Pin.
Strobe edge set by RRFB control register.
ROUT[3:0] general-purpose pins can be individually configured as either inputs or
outputs; used to control and respond to various commands.
General-purpose pins can be individually configured as either inputs or outputs;
used to control and respond to various commands.
Clock line for the bidirectional control bus communication
SCL requires an external pull-up resistor to V
Data line for bidirectional control bus communication
SDA requires an external pull-up resistor to V
I
MODE = L, Master mode; Device generates and drives the SCL clock line, where
required such as Read. Device is connected to slave peripheral on the bus.
MODE = H, Slave mode (default); Device accepts SCL clock input and attached to
an I
but uses the clock generated by the Master for the data transfers.
Device ID Address Select
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See
Power down Mode Input Pin.
PDB = H, Deserializer is enabled and is ON.
PDB = L, Deserializer is in Power Down mode. When the Deserializer is in Power
Down. Programmed control register data are NOT retained and reset to default
values.
LOCK Status Output Pin.
LOCK = H, CDR/PLL is Locked, outputs are active
LOCK = L, CDR/PLL is unlocked, the LVCMOS Outputs depend on OSS_SEL
control register, the CDR/PLL is shutdown and IDD is minimized. May be used as
Link Status.
When BISTEN = L; Normal operation
PASS is high to indicate no errors are detected. The PASS pin asserts low to
indicate a CRC error was detected on the Link.
Reserved
Pin 39: This pin MUST be tied LOW.
Pins 32,33: Route to test point or leave open if unused.
BIST Enable Pin.
BISTEN = H, BIST Mode is enabled.
BISTEN = L, BIST Mode is disabled.
2
C Mode select
2
C controller master on the bus. Slave mode does not generate the SCL clock,
6
Description
DDIO
DDIO
.
.
Table 4