DS92LV3242TVSX/NOPB National Semiconductor, DS92LV3242TVSX/NOPB Datasheet
DS92LV3242TVSX/NOPB
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DS92LV3242TVSX/NOPB Summary of contents
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... Up to 32-bit parallel LVCMOS data — MHz parallel clock — 2.72 Gbps application data paylod ■ Selectable Serial LVDS Bus Width TRI-STATE® registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation DS92LV3241/DS92LV3242 — Dual Lane Mode ( MHz) — Quad Lane Mode ( MHz) ■ ...
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Block Diagram www.national.com 2 30103627 ...
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Mode Diagrams FIGURE 1. Dual Mode FIGURE 2. Quad Mode 3 30103628 30103629 www.national.com ...
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DS92LV3241 Pin Diagram www.national.com FIGURE 3. DS92LV3241 Pin Diagram— Top View 4 30103630 ...
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DS92LV3241 Serializer Pin Descriptions Pin # Pin Name I/O, Type LVCMOS PARALLEL INTERFACE PINS 10–8, TxIN[31:29], I, LVCMOS 5–1, TxIN[28:24], 64–57, TxIN[23:16], 52–51, TxIN[15:14], 48–44. TxIN[13:9], 41–33 TxIN[8:0] 11 TxCLKIN I, LVCMOS CONTROL AND CONFIGURATION PINS 12 PDB I, LVCMOS ...
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DS92LV3242 Pin Diagram www.national.com FIGURE 4. DS92LV3242 Pin Diagram — Top View 6 30103631 ...
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DS92LV3242 Deserializer Pin Descriptions Pin # Pin Name I/O, Type LVCMOS PARALLEL INTERFACE PINS 5–7, RxOUT[31:29], O, LVCMOS Deserializer Parallel Interface Data Output Pins. 10–14, RxOUT[28:24], 19–25, RxOUT[23:17], 28–32, RxOUT[16:12], 33–39, RxOUT[11:5], 42–46 RxOUT[4:0] 4 RxCLKOUT O, LVCMOS Deserializer Recovered ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS Input Voltage LVCMOS Output Voltage LVDS Deserializer Input Voltage LVDS Driver Output Voltage Junction Temperature Storage Temperature Lead Temperature ...
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Symbol Parameter SERIALIZER LVDS DC SPECIFICATIONS V Output Differential Voltage OD ΔV Output Differential Voltage Unbalance VSEL = Offset Voltage OS ΔV Offset Voltage Unbalance OS I Output Short Circuit Current OS I TRI-STATE® Output Current OZ ...
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Symbol Parameter SERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS I Serializer (Tx) Total Supply Current DDTQ Quad Mode (includes load current) I Serializer (Tx) Total Supply Current DDTD Dual Mode (includes load current) I ...
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Symbol Parameter DESERIALIZER LVDS DC SPECIFICATIONS V Differential Threshold High Voltage TH V Differential Threshold Low Voltage TL R Input Termination T I Input Current IN DESERIALIZER SUPPLY CURRENT (DVDD*, PVDD* AND AVDD* PINS) *DIGITAL, PLL, AND ANALOG VDDS I ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t LVDS Low-to-High Transition Time LLHT t LVDS High-to-Low Transition Time LHLT t TxIN[31:0] Setup to TxCLKIN STC t TxIN[31:0] Hold from TxCLKIN HTC t ...
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Symbol Parameter Λ Jitter Transfer Function -3 dB STXBW Bandwidth δ Serializer Jitter Transfer Function STX Peaking Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Receiver Output Clock Period ROCP t RxCLKOUT ...
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Symbol Parameter t Deserializer Porpagation Delay – RD Latency t Deserializer PLL Lock Time RPLLS TOL Deserializer Input Jitter Tolerance JIT t LVDS Differential Input Skew LVSKR Tolerance Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the ...
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AC Timing Diagrams and Test Circuits FIGURE 6. Serializer Input Clock Transition Time FIGURE 7. Serializer Setup/Hold and High/Low Times FIGURE 5. Serializer LVDS Transition Times FIGURE 8. Serializer Propagation Delay 15 30103632 30103645 30103649 30103647 www.national.com ...
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FIGURE 10. Deserializer LVCMOS Output Transition Time www.national.com FIGURE 9. Serializer PLL Lock Time FIGURE 11. Deserializer Setup and Hold times FIGURE 12. Deserializer Propagation Delay 16 30103633 30103648 30103634 30103646 ...
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FIGURE 13. Deserializer PLL Lock Time and PDB TRI-STATE® Delay FIGURE 14. Deserializer TRI_STATE Test Circuit and Timing 17 30103635 30103636 www.national.com ...
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FIGURE 15. Serializer Jitter Transfer FIGURE 16. Serializer V Test Circuit Diagram OD 18 30103651 30103637 ...
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FIGURE 17. LVDS Deserializer Input Skew 19 30103638 www.national.com ...
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Functional Description The DS92LV3241 Serializer (SER) and DS92LV3242 Dese- rializer (DES) chipset is a flexible SER/DES chipset that translates a 32-bit parallel LVCMOS data bus into a quad (4 pairs) or dual (2 pairs) LVDS serial links with embedded clock. ...
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TRI-STATE® For the SER, TRI-STATE® is entered when the SER PDB pin is driven low. This will TRI-STATE® the driver output pins on TxOUT[3:0]+/-. In addition, when MODE=0 (dual mode), the TxOUT[3:2]+/- outputs pins are in TRI-STATE®. When you drive ...
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DES outputs (RxOUT[31:0]) are not available. Next, the internal test pattern generator for each channel starts transmission of the BIST pattern from SER to DES. The DES BIST mode will be automatically activated by this ...
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FIGURE 19. BIST Diagram for Different Bit Error Cases TYPICAL APPLICATION CONNECTION Figure 20 shows a typical application of the DS92LV3241 Se- rializer (SER). The differential outputs utilize 100nF coupling capacitors to the serial lines. Bypass capacitors are placed near ...
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Figure 21 shows a typical application of the DS92LV3242 Deserializer (DES). The differential inputs utilize 100nF cou- pling capacitors in the serial lines. Bypass capacitors are www.national.com FIGURE 20. DS92LV3241 Typical Connection Diagram placed near the power supply pins. A ...
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RxCLKOUT. The REN signal is not used and is tied High also. Configuration pins for the typical application are shown for DES: • PDB – Power Down Control Input – Connect to host or tie HIGH FIGURE ...
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Applications Information TRANSMISSION MEDIA The SER and DES are used in AC-coupled point-to-point configurations, through a PCB trace, or through twisted pair cables. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and connectors that have ...
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Typical Performance Characteristics The waveforms below illustrate the typical performance of the DS92LV3241. The SER was given a PCLK and configured as described below each picture. In all of the pictures the SER was configured with BISTEN pin set to ...
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Physical Dimensions Ordering Information NSID DS92LV3241TVS 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch DS92LV3241TVSX 64-Lead TQFP style, 10.0 X 10.0 X 1.0 mm, 0.5 mm pitch DS92LV3242TVS 64-Lead TQFP style, 10.0 X 10.0 X 1.0 ...
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Notes 29 www.national.com ...
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