NCN8024DWR2G ON Semiconductor, NCN8024DWR2G Datasheet - Page 10

• Manufacturer Part Number: NCN8024DWR2G
• Description: IC SMART CARD IC2 8SOIC
• Manufacturer: ON Semiconductor

Specifications of NCN8024DWR2G

• Applications: Smart Card Reader, Writer
• Voltage - Supply: 5V
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -

POWER SUPPLY
supplies: V
interface. The applied V
If V
power−down sequence is automatically performed. In that
case the interrupt (INT) pin is set Low.
followed by a Low Drop−Out (LDO) regulator is used to
provide the 3 V or 5 V power supply voltage (CRD_V
the card. V
charge−pump converter’s output. It is connected to the LDO
input. A reservoir capacitor of 100 nF is connected to VUP.
CRD_V
operate with a single output reservoir capacitor as low as
100 nF at CRD_V
of at least 320 nF in order to satisfy the datasheet
specifications. The best recommended combination
guaranteeing optimal performances consists in a distributed
set of capacitors 220 nF + 330 nF (in particular
recommended for optimally satisfying the NDS standard).
To minimize dI/dt effects, the fly capacitor (100 nF) and the
reservoir capacitors VUP and CRD_V
connected as close as possible to the corresponding device’s
pin and feature very low ESR values (lower than 50 mW).
The fly capacitor is connected between C1 and C2. The
decoupling capacitors on V
100 nF and 10 mF have also to be connected close to the
respective IC pins.
over the V
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES
NOTE:
7. Guaranteed by design and characterization
11, 12,
13, 16
9, 10
9, 10
The NCN8024 smart card interface has two power
V
A built−in charge−pump−based DC/DC converter
The CRD_VCC pin can source up to 75 mA continuously
Pin
15
16
DD
DD
is usually common to the system controller and the
CC
Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
T
I
I
Temp
Symbol
CRD_CLK
CRD_RST
goes below 2.35 V typical (UVLO
I
debounce
CRD_IO
DDP
DDP
DD
t
is the LDO output. Even if the converter can
deact
|I
|I
t
act
(V
IH
IL
and V
|
|
DD
SD
is the converter’s input voltage. VUP is the
range (from 3.3 V to 5.5 V), the absolute
CC
= 3.3 V; V
CRD_PRES, CRD_PRES
Low level input leakage current, V
CRD_PRES
CRD_PRES
High level input leakage current, V
CRD_PRES
CRD_PRES
Debounce Time CRD_PRES and CRD_PRES (Note 7)
CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation
CRD_CLK Current Limitation
CRD_RST Current Limitation
Activation Time (Note 7)
Deactivation Time (Note 7)
Shutdown Temperature
DDP
, it is recommended to use a capacitor
DD
.
DDP
ranges from 2.7 V up to 5.5 V.
DD
= 5 V; T
and V
amb
DDP
= 25°C; F
Rating
CC
have to be
respectively
IH
CLKIN
IL
VDD
http://onsemi.com
= V
= 0 V
CC
) a
DD
= 10 MHz)
) to
10
maximum current being internally limited below 150 mA
(Typical at 110 mA). CRD_VCC can stay in the range 4.6 V
– 5.30 V during current transient up to 200 mA (peak
current) over less than 400 ns of current pulse duration such
as the charge transient is lower than 40 nAs.
They can be applied to the interface in any sequence. After
powering the device INT remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
On Reset (POR) circuitry and the under voltage lockout
(UVLO) detection (V
PORADJ pin allows the user, according to the considered
application, to adjust the V
PORADJ pin is connected to Ground.
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no
further signal can be provided or supported during this
period. Such initialization takes place when the input
voltage rises between 2 V to 2.6 V about typical.
reached the minimum 2.7 V. Considering this, the NCN8024
will detect an Under−Voltage situation when the input
supply voltage will drop below 2.35 V typical. When V
goes down below the UVLO falling threshold a deactivation
sequence is performed.
the V
There’s no specific sequence for applying V
The supply voltage monitoring block includes the Power
The input supply voltage is continuously monitored to
The system is ready to operate when the input voltage has
The device is inactive during power−on and power−off of
DD
supply (8 ms reset pulse).
Min
30
30
5
−
−
−
−
DD
DD
Typ
160
5
5
8
−
−
−
−
−
voltage dropout detection).
UVLO threshold. If not used
Max
100
250
10
10
15
70
20
11
1
1
−
DD
or V
Unit
mA
mA
mA
ms
mA
°C
ms
ms
DDP
DD
.