SI2705-A10-GM Silicon Laboratories Inc, SI2705-A10-GM Datasheet
SI2705-A10-GM
Specifications of SI2705-A10-GM
Related parts for SI2705-A10-GM
SI2705-A10-GM Summary of contents
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EMI M ITIGATING Features Digital input Delta-Sigma PWM Patent-pending EMI mitigation AM radio band noise-free notch GSM/iPhone friendly Wideband PWM carrier spreading Power stage slew rate control Power stage feedback for PSR/THD 2x ...
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Si2704/05/06/07-A10 2 Rev. 0.6 ...
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... Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.3. Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4. Power Down Mode and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. Chip Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3.1. Multi-Function Pins (MFPs 4.3.2. Output Mode Configuration (Si2705/07 only 4.4. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.1. Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.4.2. Reference Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5. Digital Audio I2S Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.5.1. Auto-Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 ...
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Si2704/05/06/07-A10 8.1. 24-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Power Output Supply Voltage Main Supply Voltage Interface (I/O) Supply Voltage Load Impedance Ambient Temperature Junction Temperature Case Delta from Junction 3 Delta from Junction to Ambient Notes: 1. All ...
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Si2704/05/06/07-A10 Table 3. DC Characteristics—Supplies and Interfaces (V = 2 1. Parameter Symbol Start Up Time T ONSB T ON_SLP T ON_PD Active Mode Quiescent I PQ Supply Current ...
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Table 4. DC Characteristics—Class D Amplifier (V = 2 1. Parameter Output Voltage Offset Total Drain-Source On-State Resistance (Total Bridge)* *Note: Excludes package bond wire resistance. Table 5. AC ...
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Si2704/05/06/07-A10 Table 5. AC Characteristics—Class D Amplifier (Continued 2 1. Power Supply Rejection Ratio Crosstalk 4 Efficiency Output Pulse Repetition Frequency Notes: 1. Measured at filter output. ...
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Figure 1. Digital Audio Timing Parameters Table 8. 2-Wire Control Interface Characteristics (V = 1. –20 to +85 °C, unless otherwise noted Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input ...
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Si2704/05/06/07-A10 Table 9. 2-Wire Control Interface Address Selection CLKO Startup Voltage (Pin Table 10. Reset Timing Characteristics (V = 1. -20 to +85 °C, unless otherwise noted Parameter CLKO Setup Time to RST↑ ...
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SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 3. 2-Wire Control Interface Read and Write Timing Parameters SCLK SDIO A6-A0, 0 (Write) START ADDRESS + R/W SDIO A6-A0, 1 (Read) START ADDRESS ...
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Si2704/05/06/07-A10 Table 11. Reference Clock and Crystal Characteristics (V = 2 1. Parameter Reference Clock, Pin XTLI 1 Supported Frequencies Frequency Tolerance 2 Jitter Tolerance High Level Input Voltage ...
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... Note: When using the ferrite bead output filter with AM radio, shielded cable is recommended. Si2704/05/06/07-A10 C9 0.1 uF C10 0 OUTPL 17 OUTNL 16 U1 GNDL Si2705/07 15 GNDR 13 OUTPR 14 OUTNR C12 C13 Inductor Filter Ferrite Bead Filter 0.68 µF, ceramic 1000 pF, ceramic 0.33 µF, ceramic 1000 pF, ceramic 0.47 µ ...
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Si2704/05/06/07-A10 3. Typical System Configurations 2.7–3.6 V Supply Dock Dock I/F Stereo Line ADC In System MCU User I/F Figure 6. Basic PMP Dock System Configuration 2.7–3.6 V Supply Digital Media Controller Dock Radio Tuner Dock I/F Si473x-D Stereo Line ...
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XTLI Digital XTLO Midrange Media Amplifier Controler Si270x adress 0x36 System 2-Wire CLKO MCU XTLI Tweeter Amplifier Si270x Radio adress 0x94 Figure 8. Stereo 2-Way Speaker System Configuration ...
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Si2704/05/06/07-A10 4. Functional Description 2.7 – 3.6 V VDD Supply CLKO 1.62 – 3.6 V VIO Supply MFP System Control 2-Wire Control Figure 10. Functional Block Diagram The Si2704/05/06/07 EMI mitigating 2 Class D ...
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PWM Processing The Si270x is designed to operate using a bridge-tied-load (BTL) output configuration where both sides of the speaker are actively driven by the amplifier. 4.1.1. PWM Switching Rate Control The output PWM switching frequency can be programmed ...
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... PWM_CONFIG during normal operation without adversely affecting the internal audio processing or the differential output signal integrity. 4.1.2.4. Spectral Shaping Noise-Free Notch for AM Radio (Si2705/07 only) When using Spread Mode PWM with full rate PWM switching (960 kHz), a tunable noise-free notch can be programmed via 2-Wire control to shape the switching noise and create a narrow frequency band in the AM radio spectrum in which the PWM common mode switching energy is not allowed to spread ...
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... AM radio receiver. In normal AM radio operation, the system MCU programs the noise-free notch frequency in the Si2705/07 to the same frequency as the AM radio to inhibit PWM switching noise from interfering with radio reception. Because Spread Mode PWM is also engaged, switching noise outside of the noise-free notch band is also suppressed for mitigating broadband EMI radiation The noise-free notch can be placed at different frequencies by programming property PWM_AM_TUNE_FREQ ...
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Si2704/05/06/07-A10 POWER_DOWN Sleep Mode 4.2.2. Standby Mode Standby Mode is a reduced power state where the register states are preserved and the 2-Wire interface is fully operational, allowing for new parameters and configuration settings to be programmed even though the ...
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Standby Mode so that the high power outputs are prevented from being enabled prior to the registers being configured. Any other command sent to the device is acknowledged on the bus but ignored by the device. This mode has the ...
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... Si2704/05/06/07-A10 4.3.2. Output Mode Configuration (Si2705/07 only) The Si2705/07 can be programmed via 2-Wire or configured using the OUTSEL MFP to operate in three different output modes: 2.1 mode, 2.0 mode and aux out mode, with the 2.0 mode being the default. If OUTSEL is not configured as OUTSEL, these output modes can instead be programmed by setting the argument OUTSEL_MODE of the ACTIVATE command. Refer to the “ ...
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Figure 16. Headphone Plug Detection Application Schematic 4.4. Clocking A low jitter on-chip PLL synchronizes to an external clock reference and generates all necessary internal clocks. Three options are available for the external reference: a crystal, a reference clock or ...
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Si2704/05/06/07-A10 2 4.5. Digital Audio I S Interface The Si270x receives digital audio data using its I an input or output while DIN is restricted to input only, and all three can be configured to operate in either master or ...
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INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS I2S 0x00 1 DCLK DIN n n-1 MSB INVERTED (IFALL = 1) DCLK (IFALL = 0) DCLK DFS Left-Justified 0x03 DOUT n n-1 n-2 MSB Figure 18. Left-Justified Digital Audio ...
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Si2704/05/06/07-A10 4.6. Digital Audio Processing (DAP) The Si270x implements programmable digital audio processing which features volume control, dynamic range compressor (DRC), and audio filtering such as tone control, parametric equalization, crossover, and de-emphasis. The three channel digital audio processing chain ...
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Parametric Equalization (Si2706/07 only) The Si2706/07 includes 16 fully programmable parametric equalizer filters. Seven of these filters are implemented in each of the Left/Right main channels and the remaining two are used for the Aux Channel. The filters are ...
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Si2704/05/06/07-A10 4.6.3. De-Emphasis (Si2706/07 only) The Si2706/07 features a de-emphasis filtering option in order to be able to process recorded audio that for noise reasons has been subject to 50/15 µs pre-emphasis. The 50/15 µs filter implemented has corner frequencies ...
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Dynamic Range Compression (Si2706/07 only) The Si2706/07 features dynamic range compression (DRC) with programmable linear gain, compression threshold, compression ratio, look ahead time, attack rate, and release rate. DRC increases the net output power without clipping by decreasing the ...
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Si2704/05/06/07-A10 Figure 24. Time Domain Characteristics of the Audio Dynamic Range Controller 4.6.7. Hard Signal Limiter The device implements a hard limiter to avoid exceeding the maximum modulation rate of the amplifier. The hard limiter is always enabled. 4.6.8. DC ...
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Power Supply and Grounding Considerations Careful attention should be given to the power and ground routing to allow for optimal performance of the Si270x. The low voltage supplies, V and possible so that parasitic inductances are ...
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Si2704/05/06/07-A10 5. Commands and Properties Table 16 and Table 17 are the summary of commands and properties for the Si270x Class D Audio Amplifier device. Table 16. Class D Audio Amplifier Command Summary Number Name 0x01 POWER_UP 0x10 FUNC_INFO 0x12 ...
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Table 17. Class D Audio Amplifier Property Summary (Continued) Category Number Biquad 0x1901 CROSSOVER_FREQ Filter 0x2103 BASS_BOOST_CUT 0x2104 BASS_CORNER_FREQ 0x2105 TREBLE_BOOST_CUT 0x2106 TREBLE_CORNER_FREQ Volume 0x2201 VOLUME_MUTE 0x2202 VOLUME_MASTER 0x2203 VOLUME_BALANCE 0x2204 VOLUME_AUX_CHANNEL 0x2205 VOLUME_RAMP DRC 0x2301 DRC_CONFIG 0x2302 DRC_THRESHOLD 0x2303 ...
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... Buffered reference clock output. Configures 2-Wire address on RST. Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. ...
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... Buffered reference clock output. Configures 2-Wire address on RST. Multi-function pin 3. PWMDAC left channel analog output on Si2705/07 (Reserved on Si2704/06). PWMDAC right channel analog output on Si2705/07 (Reserved on Si2704/06). Multi-function pin 1. Output select three-level control input: 2.0, 2.1 or line out mode. Right channel power stage supply voltage. ...
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Si2704/05/06/07-A10 Table 19. Pin Descriptions (Continued) Pin Number Name 29 OUTNR 30 GNDR 31 GNDL 32 OUTNL 34 OUTPL 35 VPPL 40 RST 41 XTLO 42 XTLI 44 VDD 36 Function Right channel power stage “N” output. Right channel power ...
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... Part Number* Si2704-A10-GM 2.0 EMI Mitigating Class D Power Amplifier Si2704-A10-GQ 2.0 EMI Mitigating Class D Power Amplifier Si2705-A10-GM 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio Si2705-A10-GQ 2.1 EMI Mitigating Class D Power Amplifier with tunable noise notch for AM radio Si2706-A10-GM 2 ...
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Si2704/05/06/07-A10 8. Package Outline 8.1. 24-Pin QFN Package Figure 27 illustrates the package details for 24-pin QFN package option for the Si2704/05/06/07. Table 20 lists the values for the dimensions shown in the illustration. Table 20. 24-Pin QFN Package ...
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Package Figure 28 illustrates the package details for 48-pin eTQFP package option for the Si2704/05/06/07. Table 21 lists the values for the dimensions shown in the illustration. Si2704/05/06/07-A10 Figure 28. 48-Pin eTQFP Rev. 0.6 39 ...
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Si2704/05/06/07-A10 Table 21. 48-Pin eTQFP Package Dimensions Dimension Min Nom A — — A1 0.05 — A2 0.95 1.00 b 0.17 0.22 c 0.09 — D 9.00 BSC D1 7.00 BSC D2 3.71 3.81 e 0.50 BSC Notes: 1. All ...
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... Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week Si2704/05/06/07-A10 04 = Si2704 05 = Si2705 06 = Si2706 07 = Si2707 10 = Firmware Revision 1 Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date. ...
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... Die Revision TTTTT = Internal Code Line 3 Marking Circle = 0.5 mm Diameter (Bottom-Left Justified Year WW = Work Week 42 Si2704 Si2705 Si2706 Si2707 10 = Firmware Revision 1 Revision A Die Internal Tracking Code Pin 1 Identifier Assigned by the Assembly House. Corresponds to the year and work week of the mold date. ...
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Additional Reference Resources Si270x Evaluation Board User’s Guide AN469: 270x Programming Guide AN470: 270x Layout Guidelines AN502: Si270x Class-D Amplifier—Analog Source Setup AN503: Si270x Class-D Amplifier—Dynamic Range Compressor Use AN504: Si270x Class-D Amplifier—Dynamic ...
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Si2704/05/06/07-A10 OCUMENT HANGE IST Revision 0.4 to Revision 0.5 Updated Table 3 on page 6. Updated Table 4 on page 7. Updated Table 5 on page 7. Updated Table 6 on page 8. ...
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N : OTES Si2704/05/06/07-A10 Rev. 0.6 45 ...
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