TSL1406RS TAOS, TSL1406RS Datasheet - Page 10

• Manufacturer Part Number: TSL1406RS
• Description: Photodiodes 400 DPI SENSOR
• Manufacturer: TAOS
• Type: Linear Sensor Arrayr

Specifications of TSL1406RS

• Peak Wavelength: 1000 nm
• Maximum Rise Time: 500 ns
• Maximum Fall Time: 500 ns
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Photodiode
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TSL1406R, TSL1406RS
768 × 1 LINEAR SENSOR ARRAY WITH HOLD
TAOS042D − APRIL 2007
10
Copyright E 2007, TAOS Inc.
The minimum integration time can be calculated from the equation:
where:
In the case of the TSL1406RS with the maximum clock frequency of 8 MHz, the minimum integration time would
be:
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate
data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into
a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when
inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits
for integration time. If the amount of light incident on the array during a given integration period produces a
saturated output (Max Voltage output), then the data is not accurate. If this occurs, the integration period should
be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing
the period of time the light sampling window is active is to lower the output voltage level to prevent saturation.
However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased
by increasing the integration period provided that the maximum integration time is not exceeded. The maximum
integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated
charge. The maximum integration time should not exceed 100 ms for accurate measurements.
It should be noted that the data from the light sampled during one integration period is made available on the
analog output during the next integration period and is clocked out sequentially at a rate of one pixel per clock
period. In other words, at any given time, two groups of data are being handled by the linear array: the previous
measured light data is clocked out as the next light sample is being integrated.
Although the linear array is capable of running over a wide range of operating frequencies up to a maximum
of 8 MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock
frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required
for the analog-to-digital conversion must be less than the clock period.
n
is
the number of pixels
T
T
int(min)
int(min)
+
+ 0.125 ms
maximum clock frequency
APPLICATION INFORMATION
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(384 * 18) ) 20ms + 66.25ms
1
(n * 18) pixels ) 20ms
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