NCP3125AGEVB ON Semiconductor, NCP3125AGEVB Datasheet - Page 7

• Manufacturer Part Number: NCP3125AGEVB
• Description: Power Management Modules & Development Tools NCP3125 Evaluation Board
• Manufacturer: ON Semiconductor
• Type: DC/DC Switching Converters, Regulators & Controllersr

Specifications of NCP3125AGEVB

• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 4.5 V to 13.2 V
• Product: Power Management Modules
• For Use With/related Products: NCP3125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General
intended to supply up to a 4 A load for DC−DC conversion
from 5 V and 12 V buses. The NCP3125 is a regulator that
has integrated high−side and low−side NMOSFETs
switches. The output voltage of the converter can be
precisely regulated down to 800 mV ±1.0% when the VFB
pin is tied to V
to 350 kHz. A high gain operational transconductance
amplifier (OTA) is used for voltage mode control of the
power stage.
Duty Ratio and Maximum Pulse Width Limits
at an operating point defined by the ratio of the input to the
output voltage. The device can achieve a 75% duty ratio. The
NCP3125 has a preset off−time of approximately 150 ns,
which ensures that the bootstrap supply is charged every
switching cycle. The preset off time does not interfere with
the conversion of 12 V to 0.8 V.
Input Voltage Range (V
13.2 V with respect to GND and V
rated at 13.2 V with respect to V
26.5 V with respect to GND.
External Enable/Disable
threshold at 3 V and V
starts to rise. The V
voltage exceeds 0.9 V. Once the 0.9 V threshold is exceeded,
the part starts to switch and the part is considered enabled.
When the COMP pin voltage is pulled below the 400 mV
threshold, it disables the PWM logic, the top MOSFET is
driven off, and the bottom MOSFET is driven on. In the
disabled mode, the OTA output source current is reduced to
10 mA.
pin, an open collector or open drain drive should be used as
shown in Figure 15:
The NCP3125 is a PWM synchronous buck regulator
In steady state DC operation, the duty ratio will stabilize
The input voltage range for both V
Once the input voltage has exceeded the boost and UVLO
When disabling the NCP3125 using the COMP / Disable
OUT
. The switching frequency is internally set
SW
IN
node is tri−stated until the COMP
IN
threshold at 4 V, the COMP pin
and BST)
SW
IN
SW
, it can also tolerate
and BST is 4.5 V to
. Although BST is
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Gate Signal
Base Signal
Power Sequencing
two general purpose bipolar junction transistors or
MOSFETs. An example of the power sequencing circuit
using the external components is shown in Figure 16.
Input Voltage Shutdown Behavior
switching because the input supply reaches UVLO
threshold. Undervoltage Lockout (UVLO) is provided to
ensure that unexpected behavior does not occur when VCC
is too low to support the internal rails and power the
converter. The UVLO is set to permit operation when
converting from an input voltage of 5 V. If the UVLO is
tripped, switching stops, the internal SS is discharged, and
all MOSFET gates are driven low. The V
high impedance state and the output capacitors discharge
through the load with no ringing on the output voltage.
Power sequencing can be achieved with NCP3125 using
Input voltage shutdown occurs when the IC stops
NCP3125
COMP
Figure 15. Recommended Disable Circuits
VSW
Disable
FB1
Disable
Figure 16. Power Sequencing
Enable
Enable
1.0V
MMBT3904
VIN
2N7002E
NCP3125
COMP
VSW
SW
FB1
node enters a
COMP
COMP
3.3 V