PI6C20800SAE Pericom Semiconductor, PI6C20800SAE Datasheet - Page 2

• Manufacturer Part Number: PI6C20800SAE
• Description: Clock Buffer Clock Buffer 3.3V/5V 160MHz
• Manufacturer: Pericom Semiconductor

Specifications of PI6C20800SAE

• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
Serial Data Interface (SMBus)
PI6C20800S is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7-bit
address and read/write bit as shown below.
Address assignment
Data Write Protocol
Note:
1.
SRC_DIV#
SRC & SRC#
OE [0:7]
OE_INV
OUT[0:7] & OUT[0:7]#
PLL/BYPASS#
SCLK
SDA
I
SRC_STOP#
PLL_BW#
PWRDWN#
LOCK
V
V
V
V
Start
1 bit
REF
bit
DD
SS
SS_A
DD_A
Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.
A6
1
Pin Name
10-0150
7 bits
Slave
Addr
W
A5
1
1
(1)
Ground
Ground
Ack
Output
Output
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
1
I/O
Register
offset
8 bits
A4
0
20, 21, 29, 30, 33, 34,
6, 7, 14, 15, 35, 36,
8, 9, 12, 13, 16 17,
2, 11, 19, 31, 39
3, 10, 18, 25, 32
37, 38, 41, 42
43, 44
Ack
Pin #
4, 5
1
40
22
23
24
46
27
28
26
45
47
48
1
A3
1
Count
8 bits
Byte
= N
3.3V LVTTL input for selecting input frequency divide by 2,
active LOW.
0.7V Differential SRC input from PI6C410 clock synthesizer
3.3V LVTTL input for enabling outputs, active HIGH.
3.3V LVTTL input for inverting the OE, SRC_STOP# and
PWRDWN# pins.
When 0 = same stage
When 1 = OE[0:7], SRC_STOP#, PWRDWN# inverted.
0.7V Differential outputs
3.3V LVTTL input for selecting fan-out of PLL operation.
SMBus compatible SCLOCK input
SMBus compatible SDATA
External resistor connection to set the differential output current
3.3V LVTTL input for SRC stop, active LOW
3.3V LVTTL input for selecting the PLL bandwidth
3.3V LVTTL input for Power Down operation, active LOW
3.3V LVTTL output, transition high when PLL lock is achieved
(Latched output)
3.3V Power Supply for Outputs
Ground for Outputs
Ground for PLL
3.3V Power Supply for PLL
2
Ack
1
A2
1
Offset
8 bits
Data
Byte
A1
1
Ack
1
Descriptions
Byte N
8 bits
Data
- 1
A0
0
HCSL Clock Buffer
Ack
1
PCI Express
PS8887D
Stop bit
1 bit
PI6C20800S
R/W
0/1
®
03/29/10
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