73M1916-IVT/F Maxim Integrated Products, 73M1916-IVT/F Datasheet
73M1916-IVT/F
Specifications of 73M1916-IVT/F
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73M1916-IVT/F Summary of contents
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... The 73M1966B device set consists of the 73M1906B Host-Side Device that provides digital data, control interfaces and power to the 73M1916 Line-Side Device. These devices are based on an innovative and patented technology, which sets new standards in reliability and cost. A small pulse transformer ...
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... Interface Timing Specification................................................................................................ 18 3.3.1 SPI Interface ............................................................................................................. 18 3.3.2 PCM Highway Interface ............................................................................................. 19 3.4 Analog Specifications ............................................................................................................ 20 3.4.1 DC Specifications ...................................................................................................... 20 3.4.2 Call Progress Monitor ................................................................................................ 21 3.5 73M1x66B Line-Side Electrical Specifications (73M1916) ...................................................... 22 3.6 Reference and Regulation ..................................................................................................... 23 3.7 DC Transfer Characteristics .................................................................................................. 23 3.8 Transmit Path ....................................................................................................................... 24 3.9 Receive Path ........................................................................................................................ 25 3.10 Transmit Hybrid Cancellation ................................................................................................ 26 3 ...
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DS_1x66B_001 8.5 Transmit and Receive Levels ................................................................................................ 48 8.5.1 A-Law........................................................................................................................ 48 8.5.2 μ-Law ........................................................................................................................ 48 8.5.3 Transmit and Receive Level Control .......................................................................... 48 8.6 Transmit Path Signal Processing ........................................................................................... 49 8.6.1 General Description ................................................................................................... 49 8.6.2 Total Transmit Path Response................................................................................... ...
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... Figure 2: 73M1906B 20-Pin TSSOP Pinout .............................................................................................. 8 Figure 3: 73M1916 20-Pin TSSOP Pinout ................................................................................................ 9 Figure 4: 73M1906B 32-Pin QFN Pinout ................................................................................................ 10 Figure 5: 73M1916 32-Pin QFN Pinout .................................................................................................. 12 Figure 6: 73M1866B 42-Pin Pinout ........................................................................................................ 14 Figure 7: SPI Timing Diagram ................................................................................................................ 18 Figure 8: PCM Timing Diagram for Positive Edge Transmit Mode and Negative Edge Receive Mode ..... 19 Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode ...
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... Tables Table 1: 73M1906B 20-Pin TSSOP Pin Definitions .................................................................................. 8 Table 2: 73M1916 20-Pin TSSOP Pin Definitions ..................................................................................... 9 Table 3: 73M1906B 32-Pin QFN Pin Definitions ..................................................................................... 10 Table 4: 73M1916 32-Pin QFN Pin Definitions ....................................................................................... 12 Table 5: 73M1866B Pin Definitions ........................................................................................................ 14 Table 6: Isolation Barrier Characteristics ................................................................................................ 16 Table 7: Absolute Maximum Device Ratings .......................................................................................... 16 Table 8: Recommended Operating Conditions ....................................................................................... 16 Table 9: DC Characteristics ...
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... PSTN. The device set supports ITU-T Recommendation G.711 µ-law and A-law companding, and also a 16-bit linear mode. High-voltage isolation is provided by the physical separation of the Host-Side (73M19106) and Line-Side (73M1916) Devices. The Host-Side and the Line-Side Devices communicate with each other using a single pulse transformer. A few low-cost components complete the DAA interface to the network ...
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... DS_1x66B_001 The Line-Side Device (73M1916) consists of: 1. Digital Sigma Delta Modulator 2. Transmit Analog Front End 3. Receive Analog Front End including Sigma Delta Modulator 3 4. Sinc Filter (Sinc3) 5. On-chip Line Interface Circuit 6. Line-Side Barrier Interface Circuit (LSBI) Received data from a host connected to the PCM bus is interpolated from the sampling frequency of 8 kHz or 16 kHz (for PCM encoded streams) to twice the sampling frequency ...
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... Data Sheet 2 Pinout The 73M1906B and the 73M1916 are supplied as 20-pin TSSOP packages and as 32-pin QFN packages. 2.1 73M1906B 20-Pin TSSOP Pinout Figure 2 shows the 73M1906B 20-pin TSSOP pinout. CS VPD PCLKO PCLKI VNA/VND AOUT VPA Figure 2: 73M1906B 20-Pin TSSOP Pinout Table 1 describes the pin functions for the device ...
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... DS_1x66B_001 2.2 73M1916 20-Pin TSSOP Pinout Figure 3 shows the 73M1916 20-pin TSSOP pinout. DCI RGN RGP OFH VNX SCP MID VPX SRE SRB Figure 3: 73M1916 20-Pin TSSOP Pinout Table 2 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins ...
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Data Sheet 2.3 73M1906B 32-Pin QFN Pinout Figure 4 shows the 73M1906B 32-pin QFN pinout. GPIO7 TSC DX VPD FS PCLKO PCLKI VND Figure 4: 73M1906B 32-Pin QFN Pinout Table 3 describes the pin functions for the device. Decoupling ...
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DS_1x66B_001 Pin Pin Name Type Number 17 PRM I/O 18 PRP I/O 19 VPT PWR 20 VPD PWR RST SDIT O 23 SDI I 24 SDO O I/O 25 GPIO5 GND 26 VND INT ...
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... Data Sheet 2.4 73M1916 32-Pin QFN Pinout Figure 5 shows the 73M1916 32-pin QFN pinout. CKO 1 OFH 2 3 CKI VNX SCP 5 MID SCM 8 VPX Table 4 describes the pin functions for the device. Decoupling capacitors on the power supplies should be included for each pair of supply pins. ...
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DS_1x66B_001 Pin Pin Type Number Name 16 VNS GND 17 VPS PWRO 18 RXP I 19 RXM I 20 SACIN I 21 TXM O TST 22 I RST DCD O 25 DCS I 26 DCG O 27 ...
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Data Sheet 2.5 73M1866B Pinout Figure 6 shows the 73M1866B 42-pin pinout VPD PCLKO 5 VNA 6 PCLKI 7 AOUT 8 VPA 9 VNT 10 PRM Table 5 describes the pin functions for ...
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DS_1x66B_001 Pin Pin Name Type Number 17 GND VND INT SCLK SRE O 23 SRB O 24 VBG 25 I ACS 26 GND VNS PWRO Analog positive supply ...
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Data Sheet 3 Electrical Characteristics and Specifications 3.1 Isolation Barrier Characteristics Table 6 provides the characteristics of the 73M1x66B Isolation Barrier. Table 6: Isolation Barrier Characteristics Parameter Barrier frequency Data transfer rate across the barrier for the sampling rate ...
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... IDD current IDD4 SLEEP=1 (Ext Ref Clk) IDD current IDD6 ENFEH=0 (Ext Ref Clk) *Note: IDD1 is with the secondary of the barrier left open. IDD2 is with the secondary of the barrier connected to 73M1916 fully powered. Rev. 1.6 Table 9: DC Characteristics Condition Min – -0.5 – ...
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Data Sheet 3.3 Interface Timing Specification There are three interfaces associated with the 73M1x66B: the SPI interface, the PCM highway interface and the line interface. This section provides the timing specification for the SPI interface and the PCM highway ...
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DS_1x66B_001 3.3.2 PCM Highway Interface Table 11: Switching Characteristics – PCM Interface (Slave Mode) Parameter PCLK_IN cycle time PCLK_IN rise time PCLK_IN fall time FS setup time FS hold time FS cycle time DR setup time DR hold time DX ...
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Data Sheet PCLK t t ifs ifh FS t ird odd DX Figure 9: PCM Timing Diagram for Negative Edge Transmit Mode and Positive Edge Receive Mode 3.4 Analog Specifications This section provides the electrical characterizations ...
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DS_1x66B_001 3.4.2 Call Progress Monitor The Call Progress Monitor monitors activities on the line. The audio output contains both transmit and receive data with a configurable level individually set by Register 10h. Figure 10 shows the frequency response of the ...
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... AOUT receive THD CMRXG=00 AOUT output impedance 3.5 73M1x66B Line-Side Electrical Specifications (73M1916) Table 16 lists the absolute maximum ratings for the line side. Operation outside these rating limits may cause permanent damage to this device. Table 16: Line-Side Absolute Maximum Ratings Parameter Pin input voltage from VPX to VNX ...
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DS_1x66B_001 3.6 Reference and Regulation Table 17 lists the VBG specifications. VBG should be connected to an external bypass capacitor with a minimum value of 0.1 μF. This pin is not intended for any other external use. The following conditions ...
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Data Sheet 3.8 Transmit Path Table 19 list the transmit path characteristics. A pattern for a sinusoid of 1 kHz, full scale (code word of +/- 32,767) from the 73M1x66B is forced and ACS is measured with R10=174 Ω. ...
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DS_1x66B_001 3.9 Receive Path Table 20 lists the receive path characteristics. All test inputs are driven through an AC coupling network shown in Figure 29. The receive bit stream is measured at the DX pin. RXEN=1. Parameter Differential input resistance ...
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... Transmit Hybrid Cancellation Table 21 lists the transmit hybrid cancellation characteristics. Unless stated otherwise, test conditions are: ACZ[3:0]=0000 (600 Ω termination), THEN=1, ATEN=1, DAA[1:0]=01, TXBST=0. TXM is externally fed back into the 73M1916 to effect cancellation of transmit signal. Table 21: Transmit Hybrid Cancellation Characteristics Parameter ...
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DS_1x66B_001 3.12 Detectors This section provides electrical characteristics for the following detectors: • Over-Voltage. • Over-Current. • Under-Voltage. • Over-Load. 3.12.1 Over-Voltage Detector The values in Table 23 were measured between RGP and RGN. Parameter Test Condition Over voltage levels ...
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... SCP SCP RXP 7 14 MID VPS 8 13 VPX VNS C10 C26 9 12 SRE ACS 3 0.22uF 1nF 10 11 SRB VBG U1 73M1916-20 C9 C20 0.22uF 1nF R6 17.4K, 1% SRB SRE 1 52.3K, 1% MMBTA06 TP15 VPS C37 0.01uF C12 R10 C8 C38 0.1uF + 0.1uF 174, 1% 4.7uF ISOLATION BARRIER ...
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DS_1x66B_001 1 Q5 MMBTA06 C37 0.01uF 17.4K, 1% R10 174, 1% C12 0.1uF VNS Maintain 2.5 mm Spacing Between Line and Host Side Components PCM TX 21 73M1866B DR SPI CSB 20 CS SPI CLK 19 SCLK INTB 18 INT ...
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Data Sheet 4.2 Bill of Materials Table 27 provides the 73M1x66 bill of materials for the reference schematics provided in Figure 12 and Figure 13. Table 27: Reference Bill of Materials for 73M1x66B Qty Reference 1 BR1 HD04 rectifier ...
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DS_1x66B_001 4.3 Over-Voltage and EMI Protection Over-voltage protection is required to meet worst-case conditions for target countries. UL1950, EN60950, IEC 60950, ITU-T K.20/K.21 and GR-1089-CORE specifications define the protection requirements for many countries. A single design can be implemented to ...
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Data Sheet 4.4 Isolation Barrier Pulse Transformer The isolation element used by the 73M1x66B is a standard digital pulse transformer. Several vendors supply compatible transformers with up to 6000 V ratings. Since the transformer is the only component crossing ...
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DS_1x66B_001 5 SPI Interface The host accesses the 73M1x66B using an SPI interface to write to control registers and read status registers. The host is the master of the transaction. Four pins orchestrate the communication between the host and the ...
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Data Sheet SDO HOST The R/W bit determines whether the host requests a read ( write (0) operation. The second byte of the SPI transaction is the address byte. The address byte simply contains the 8-bit value ...
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DS_1x66B_001 CS SCLK SDI CONTROL SDO Figure 17: SPI Read Transaction – 8-bit Mode In 16-bit mode, the first frame of 16 bits contains both the control and address bytes, and the second frame contains the data bytes. Note that ...
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Data Sheet • In 8-bit mode, if either the control or the address frames do not correspond to a multiple of eight SCLK cycles, the SPI state machine resets and the transaction is aborted. If the data frame is ...
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DS_1x66B_001 6 Control and Status Registers Table 31 shows the 73M1x66B register map of addressable registers. The shaded cells indicate read-only bits and cannot be modified. Reserved bits should be left in their default state. Accessing unspecified registers should be ...
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Data Sheet Throughout this document, type W is read/write, type WO is write only and type R is read only. Registers and bits are defined as 0x16[3:0], where 0x16 is the register address and the numbers in square brackets ...
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DS_1x66B_001 Bit Name Register Page LV 0x1B[7:1] 76 MASTER 0x23[6] 52 MATCH 0x19[6] 41 OFH 0x12[7] 70 OIDET 0x1E[4] 77 OLDET 0x1E[3] 77 OVDET 0x1E[5] 77 OVDTH 0x13[2] 77 PCLKDT 0x03[4] 52 PCMEN 0x23[7] 52 PCODE 0x23[5:2] 53 PLDM 0x13[3] ...
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Data Sheet While all registers may be read or written to via an SPI operation without error, some registers react differently to read and write operations, as follows: • Read/Write (W) registers change in response to an SPI write ...
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... These read only status bits indicate the revision of the 73M1x66B Host-Side Device (73M1906B). Line-Side Device Revision These read-only status bits provide the Device ID for the 73M1x66B Line-Side Device (73M1916). When barrier is synchronized, REV has the value of 1101. When barrier is not synchronized, the value of the field is 0000. 4 ...
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Data Sheet 7.3 Power Management The 73M1x66B supports three modes of power control for the device. Normal mode The 73M1x66B operates normally. ENFEH = 0 In this mode the Host Side of the Barrier interface is disabled and the ...
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DS_1x66B_001 7.5 GPIO Registers Three user-defined I/O pins are provided in the 32-pin QFN package of the 73M1966B only. The pins are GPIO7, GPIO6 and GPIO5. GPIO pins are not available on the 20-pin package of the 73M1966B. GPIO pins ...
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Data Sheet 7.6 Call Progress Monitor the purpose of monitoring activities on the line, a Call Progress Monitor is provided in the 73M1x66B. For This audio output contains both transmit and receive data with configurable levels. Function Register Type ...
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DS_1x66B_001 8 PCM Highway Interface and Signal Processing The PCM highway is the method by which the 73M1x66B exchanges PCM data with the host or other PCM-enabled devices. The PCM data can be in either 8-bit compressed mode or in ...
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Data Sheet FS PCLK DX MSB Figure 21: 16-bit Transmission Example Similarly, the 16-bit data sample is received most significant bit first, beginning at the bit slot defined by the RTS and RCS control registers. The reception lasts for ...
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DS_1x66B_001 8.2 PCM Clock Frequencies The 73M1x66B supports the following PCLK input frequencies: • 256 kHz • 512 kHz • 768 kHz • 1.024 MHz • 1.536 MHz • 1.544 MHz • 2.048 MHz • 3.088 MHz • 4.096 MHz ...
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Data Sheet 8.5 Transmit and Receive Levels 8.5.1 A-Law According to the ITU-T Recommendation G.711, A-law assumes +4096 (in sign plus 12 bit) to represent 3.14 dBm. That is, a sinusoid having a peak value of +4095 to correspond ...
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DS_1x66B_001 8.6 Transmit Path Signal Processing 8.6.1 General Description In the transmit path, data is first sent by the host DSP through a serial interface to the 73M1x66B then interpolated by an interpolation filter, serialized and transmitted across barrier interface ...
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Data Sheet 8.6.3 73M1x66B Transmit Spectrum Figure 28 shows the transmit spectrum observed on the line from kHz for a sample frequency (Fs kHz. The transmit signal is band-limited (by default) to Fs/2=4 kHz ...
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DS_1x66B_001 8.7.2 Total Receive Path Response Figure 29: Overall Frequency Response of the Receive Path Figure 30: Pass-band Response of the Overall Receive Path 8.7.3 Receiver DC Offset Subtraction The 73M1x66B provides a method to improve audio quality by reducing ...
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Data Sheet 8.8 PCM Control Functions Function Register Type Mnemonic Location ADJ 0x22[6] W DAA 0x14[6:5] W ENPCLKDT 0x05[4] W LAW 0x23[0] W LIN 0x23[1] W MASTER 0x23[6] W PCLKDT 0x03[4] R PCMEN 0x23[ Table 33: PCM ...
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DS_1x66B_001 Function Register Type Mnemonic Location PCODE 0x23[5:2] W RCS 0x22[5:3] W RPOL 0x21[7] W RTS 0x21[6:0] W Rev. 1.6 Description PCM Clock Code The default state of PCODE out of reset is 0000. In PCM Slave Mode at reset, ...
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Data Sheet Function Register Type Mnemonic Location RXDG 0x09[7:0] WO RXEN 0x16[6] W RXG 0x14[1:0] W RXOCEN 0x17[5] W RXOM 0x25[7: Description Receiver Digital Gain These bits controls the value of the digital gain section of the ...
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DS_1x66B_001 Function Register Type Mnemonic Location SEL16K 0x13[ 0x22[7] W TCS 0x22[2:0] W TPOL 0x20[7] W TTS 0x20[6:0] W TXBST 0x14[7] WO Rev. 1.6 Description Sample Rate Mode Configuration Select Configures the 16 kHz mode of operation. See ...
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Data Sheet Function Register Type Mnemonic Location TXDG 0x08[7:0] WO TXEN 0x16[ Description Transmitter Digital Gain These bits control the value of the digital gain section of the 73M1x66B transmit path. Each bit indicates either a gain ...
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DS_1x66B_001 8.8.1 Transmit and Receive Level Control Refer to Section 8.5 for information about 73M1x66B levels. 8.8.1.1 Transmit Gain Scaling The first gain stage in the transmit signal path is the digital gain whose value is controlled by writing to ...
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Data Sheet TX Level dBm TxBst DAA1 DAA0 dB -17 0 -16 0 -15 0 -14 0 -13 0 -12 0 - ...
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DS_1x66B_001 Table 36 lists the value of Receive Gain for each value of RXG. The precise values of the digital gain settings are: Bit 7 Gain 0.25 Gain / Attenuation -12.04dB 8.8.1.3 Maximum Levels The 73M1x66B is capable of providing ...
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Data Sheet 9 Barrier Information 9.1 Isolation Barrier The 73M1x66B uses the Teridian MicroDAA proprietary isolation method based upon low-cost pulse transformer coupling. This technique provides several advantages over other methods, including: • Lower BOM cost. • Reduced component ...
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DS_1x66B_001 Upon power up, the following sequence should be used to ensure barrier synchronization: 1. The 73M1906B starts in Barrier Powered Mode and transmits a preamble to aid the PLL locking of the Line-Side Device. 2. When PLL Lock detect ...
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Data Sheet Function Register Type Mnemonic Location RSTLSBI 0x0D[3] W SLHS 0x0D[6] R SLLS 0x1E[2] R SYNL 0x03[ Description Reset Line-Side Barrier Interface To reset the Line-Side Barrier Interface, set this bit Resets ...
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... SRB VBG 73M1916-20 Figure 32: Line-Side Device AC and DC Circuits The DCIV bits control the voltage versus current characteristics of the 73M1x66B by monitoring the voltage at the line divided down by the ratios of (R3+R4)/R4 (5:1) measured at the DCI pin. This voltage does not include the voltage across the Q4 and the bridge. When both the ENAC and ENDC bits are set (the hold mode), the DCIV characteristics follow approximately a 50 Ω ...
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Data Sheet 10 Configurable Direct Access Arrangement (DAA) The 73M1x66B Line-Side Device integrates most of the circuitry to implement a PSTN line interface or DAA that is capable of being globally compliant with a single bill of materials. The ...
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DS_1x66B_001 The 73M1x66B can: • Shift the characteristics by setting the turn-on voltage. • Enable a current limit of 42 mA. The 73M1x66B meets a wide range of different countries’ requirements under software control. See Section 10.7. There are two ...
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Data Sheet An example of the use of the Seize state is for Australia, which requires this state for the first 300 ms immediately after going off hook. 14 Australian 12 Prohibited Region ...
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DS_1x66B_001 ⋅ F1db f 1000 ( ) 0.5 0 Figure 36: Magnitude Response of Impedance Matching Filter, ACZ (3:0)=0010 (ES 203 021-2) 10.4 Billing Tone Rejection ...
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Data Sheet 10.5 Trans-Hybrid Cancellation In order to improve performance, the Trans-hybrid Cancellation option allows a replica of the transmit signal to be created within the 73M1x66B and fed back to the RXM pin via an external circuit at ...
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DS_1x66B_001 Function Register Type Mnemonic Location ATEN 0x16[4] W DCIV 0x13[7:6] W ENAC 0x12[5] WO ENDC 0x12[6] WO ENFEL 0x12[2] WO Rev. 1.6 Description Active Termination Loop Enable Enables or disables Active Termination Loop Disable. (Default ...
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... Disable LeV detection (used in line-powered mode to save power). This bit will be 0 when Line Powered Mode is detected (ENLPW is set in Register 0x02[2]) and set to 1 when an interrupt occurs within the 73M1916. This bit must be reset prior to switching back to Barrier Powered Mode. Enable Nominal Operation ...
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DS_1x66B_001 Function Register Type Mnemonic Location RLPNH 0x14[2] W THEN 0x15[3] W Rev. 1.6 Description Receive Low Pass Notch 0 = Selects Receive Low Pass Notch (RLPN kHz. (Default Selects RLPN at 16 kHz. See RLPNEN ...
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Data Sheet 10.7 International Register Settings Table for DC and AC Terminations Table 39 lists the recommended ACZ and DCIV register settings for various countries. Other parameters can also be set in addition to the AC and DC termination. ...
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... It is also possible to receive Caller ID signals while the telephone is in use, referred to as Type II CID. This requires the 73M1916 to constantly monitor the line for signals, such as special in-band or CAS tones, while the FXO is in the off-hook state. This is done through the normal receive path. ...
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Data Sheet 11.7 Voltage and Current Detection The 73M1x66B is capable of detecting the following circumstances: • Under voltage on the line. • Over voltage on the line. • Over current. These 73M1x66B built-in mechanisms provide protection to both ...
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DS_1x66B_001 11.12 Line Sensing Control Functions These registers contain control information to set up and use the 73M1x66B line sensing functions. Table 40: Line Sensing Control Functions Function Register Type Mnemonic Location CIDM 0x15[4] W RXBST 0x14[3] WO ENRGDT 0x05[0] ...
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Data Sheet Function Register Type Mnemonic Location LC 0x1C[7: 0x1B[7:1] R RNG 0x1A[7:0] R DET 0x03[2] R ENDET 0x05[2] W ENDT 0x12[1] WO Under-Voltage Detection Control and Status ENUVD 0x15[2] WO UVDET 0x1E[ Description Auxiliary ...
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DS_1x66B_001 Function Register Type Mnemonic Location Over-Voltage Detection Control and Status ENOVD 0x15[1] WO OVDET 0x1E[5] R OVDTH 0x13[2] WO ENOLD 0x15[7] WO OLDET 0x1E[3] R Over-Current Detection Control and Status ENOID 0x15[0] WO OIDET 0x1E[4] R Rev. 1.6 Description ...
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... Table 41 describes how the above control bits interact to provide each of the six loopback modes. TEST TMEN DTST 0000 0 0000 0 0000 1 0000 1 0001 0 0010 0 0011 0 78 73M1916 STA Aux A/D PRP SCP DSDM LSBI DIGLB2 SinC3 Filter PRM SCM Table 41: Loopback Modes LB Loopback Mode Normal Mode. (Default Loopback between PCM Compander ...
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DS_1x66B_001 12.1 Loopback Controls Table 42 describes the registers used for loopback control. Function Register Mnemonic Location TMEN 0x02[7] DTST 0x07[1:0] LB 0x24[0] TEST 0x18[7:4] Rev. 1.6 Table 42: Loopback Controls Type W Test Mode Enable Used to enable the ...
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Data Sheet 13 Performance This section provides an overview of typical performance characteristics measured using 73M1x66B production devices on a Teridian Reference Board. The measurements were made using a Wandel and Goltermann PCM-4 test unit. The tests conform to ...
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DS_1x66B_001 Figure 41 provides performance characteristics for receive gain variation against frequency. Figure 41: Gain versus Frequency for Digital Input to Analog Output at the Line Figure 42 provides performance characteristics for distortion in the direction of the digital port ...
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Data Sheet 13.2 Receive Figure 43 provides performance characteristics for receive gain tracking. Figure 43: Variation of Receiver Analog Gain at the Line to the Digital DX Output 82 DS_1x66B_001 Rev. 1.6 ...
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DS_1x66B_001 Figure 44 provides performance characteristics for gain variation against frequency. Figure 44: Gain versus Frequency for Analog Input at the Line to the Digital DX Output Figure 45 provides performance characteristics for distortion in the direction of the analog ...
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Data Sheet 84 Figure 46: Return Loss DS_1x66B_001 Rev. 1.6 ...
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DS_1x66B_001 14 Package Layout Figure 47: 20-Pin TSSOP Package Dimensions 5 2 TOP VIEW 3.0 / 3.75 0.18 / 0.3 1.5 / 1.875 0.2 MIN. 0.35 / 0.45 0.25 0.5 BOTTOM VIEW Figure 48: 32-Pin QFN Package ...
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Data Sheet Figure 49: 42-Pin QFN Package Dimensions 86 DS_1x66B_001 Rev. 1.6 ...
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... For a complete list of worldwide sales offices http://www.teridian.com. Rev. 1.6 73M1866B/73M1966B Data Sheet Order Number Packaging Mark 73M1966B-IM/F 73M1916A-M 73M1906B 73M1966B-IMR/F 73M1916A-M 73M1906B 73M1966B-IVT/F 73M1916AVT 73M1906BVT 73M1966B-IVTR/F 73M1916AVT 73M1906BVT 73M1866B-IM/F 73M1866B-IM 73M1866B-IMR/F 73M1866B-IM Host/Line Line-Side IC Host-Side IC Line-Side IC Host-Side IC Line-Side IC Host -Side IC Line-Side IC Host -Side IC ...
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Data Sheet Revision History Revision Date 1.0 11/7/2007 First publication. 1.1 5/13/2008 1.2 7/30/2008 1.3 11/17/2008 1.4 7/21/2009 1.5 10/16/2009 1.6 4/2/2010 Replaced Table 16 with a new table. Replaced the schematics in Figure 12 and Figure 13 with ...