TC7W74FUTE12LF Toshiba, TC7W74FUTE12LF Datasheet

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TC7W74FUTE12LF

Manufacturer Part Number
TC7W74FUTE12LF
Description
Flip Flops x34 D FLIP-FLOP
Manufacturer
Toshiba
Datasheet

Specifications of TC7W74FUTE12LF

Number Of Circuits
1
Logic Family
HC
Logic Type
CMOS
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
150 ns
High Level Output Current
- 5.2 mA
Supply Voltage (max)
6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
D-Type Flip Flop with Preset and Clear
with silicon gate C
LSTTL while maintaining the C
OUTPUT during the positive going transition of the CLOCK pulse
CLEAR and PRESET are independent of the CLOCK and are
accomplished by setting the appropriate input to an “L” level
Input is equipped with protection circuits against static discharge
or transient excess voltage.
Features
Marking
The TC7W74 is a high speed C
It achieves the high speed operation similar to equivalent
The signal level applied to the D INPUT is transferred to Q
High speed: f
Low power dissipation: I
High noise immunity: V
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |I
Balanced propagation delays: t
Wide operating voltage range: V
TC7W74F,TC7W74FU,TC7W74FK
TC7W74F
TC7W74FU
TC7W74FK
7 W 7 4 F
7 W 7 4
W
7 4
max
2
MOS technology.
= 77 MHz (typ.) at V
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
NIH
Part No.
CC
Part No.
Lot No.
= 2 μA (max) at Ta = 25°C
= V
2
Part No.
Lot No.
2
MOS low power dissipation.
MOS D Flip Flop fabricated
pLH
NIL
CC
OH
∼ − t
(opr) = 2 to 6 V
= 28% V
CC
| = I
pHL
= 5 V
OL
CC
= 4 mA (min)
(min)
1
Weight
SOP8-P-1.27: 0.05 g (typ.)
SSOP8-P-0.65: 0.02 g (typ.)
SSOP8-P-0.50A: 0.01 g (typ.)
TC7W74F
TC7W74FU
TC7W74FK
TC7W74F/FU/FK
2009-09-30

Related parts for TC7W74FUTE12LF

TC7W74FUTE12LF Summary of contents

Page 1

... TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7W74F,TC7W74FU,TC7W74FK D-Type Flip Flop with Preset and Clear The TC7W74 is a high speed C MOS D Flip Flop fabricated 2 with silicon gate C MOS technology achieves the high speed operation similar to equivalent LSTTL while maintaining the C MOS low power dissipation. ...

Page 2

... Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test report and estimated failure rate, etc) ...

Page 3

Truth Table Inputs CLR Operating Ranges Characteristics Supply voltage Input voltage Output voltage Operating temperature range Input rise and fall ...

Page 4

Timing Requirements (input t Characteristics Symbol t Minimum pulse width W (L) (CLOCK (H) Minimum pulse width t W (L) ( CLR , PR ) Minimum set-up time t s Minimum hold time t h Minimum removal time ...

Page 5

AC Electrical Characteristics Characteristics Symbol t TLH Output transition time t THL Propagation delay time t pLH (CLOCK- pHL Propagation delay time t pLH t ( CLR , PR - pHL Maximum clock frequency f ...

Page 6

Package Dimensions Weight: 0.05 g (typ.) TC7W74F/FU/FK 6 2009-09-30 ...

Page 7

Package Dimensions Weight: 0.02 g (typ.) TC7W74F/FU/FK 7 2009-09-30 ...

Page 8

Package Dimensions Weight: 0.01 g (typ.) TC7W74F/FU/FK 8 2009-09-30 ...

Page 9

... Product shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. • The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise. • ...

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