DS3065WP-100IND+ Maxim Integrated Products, DS3065WP-100IND+ Datasheet - Page 14

• Manufacturer Part Number: DS3065WP-100IND+
• Description: NVRAM 3.3V 8MB NONVOLATILE SRAM W/CLK
• Manufacturer: Maxim Integrated Products

Specifications of DS3065WP-100IND+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

When the RTC register values match alarm register set-
tings, the alarm flag (AF) is set to a 1. If AE is also a 1,
the alarm condition activates the IRQ/FT output. When
CS is active, the IRQ/FT signal can be cleared by hold-
ing the FLAGS register address stable for t
ing either OE or WE active (see Figure 1). The flag does
not change state until the end of the read/write cycle
and after the IRQ/FT signal has deasserted. To avoid
inadvertently clearing the IRQ/FT signal while preparing
for subsequent write/read cycles at other register
addresses, assure that t
address (see Figure 2).
3.3V Single-Piece 256kb Nonvolatile SRAM
with Clock
Table 3. Alarm Mask Bits
Figure 1. Clearing Active IRQ Waveforms
14
AM4
WE OR OE
____________________________________________________________________
1
1
1
1
0
A0–A3
IRQ/FT
CE
CS
AM3
1
1
1
0
0
AW
is met for that subsequent
AM2
1
1
0
0
0
RC
and forc-
AM1
1
0
0
0
0
ADDRESS 0h
t
RC
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
MAX
The IRQ/FT output can also be activated during battery
backup mode. The IRQ/FT goes low if an alarm occurs
and both AE and ABE are set to 1. The AE and ABE
bits are reset to 0 during the power-up transition, but an
alarm generated during power-up will set AF to a 1.
Therefore, the AF bit can be read after system power-
up to determine if an alarm was generated during the
power-up sequence. Figure 3 illustrates alarm timing
during battery backup mode and power-up states.
ALARM RATE
HIGH IMPEDANCE