ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 7

• Manufacturer Part Number: ATTINY861-20PU
• Description: Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY861-20PU

• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Package / Case: PDIP-20
• Controller Family/series: AVR Tiny
• Core Size: 8 Bit
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Ram Size: 512 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4. CPU Core
4.1
2588E–AVR–08/10
Architectural Overview
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
Figure 4-1.
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the Program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
tion is pre-fetched from the Program memory. This concept enables instructions to be executed
in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.
Control Lines
Instruction
Instruction
Program
Memory
Decoder
Register
Flash
Block Diagram of the AVR Architecture
Program
Counter
and Control
EEPROM
Registrers
I/O Lines
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
I/O Module 2
Comparator
I/O Module1
I/O Module n
Watchdog
Interrupt
Timer
Analog
Unit
7