MAX5974CETE+ Maxim Integrated Products, MAX5974CETE+ Datasheet - Page 4

• Manufacturer Part Number: MAX5974CETE+
• Description: Current Mode PWM Controllers ACTIVE-CLAMPED CUR MODE PWM CONTLR
• Manufacturer: Maxim Integrated Products

Specifications of MAX5974CETE+

• Duty Cycle (max): 82 %
• Mounting Style: SMD/SMT
• Switching Frequency: 600 KHz
• Operating Supply Voltage: 12 V to 21 V
• Supply Current: 1.8 mA
• Maximum Operating Temperature: + 85 C
• Fall Time: 14 ns
• Minimum Operating Temperature: - 40 C
• Rise Time: 27 ns
• Package / Case: TQFN-16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Active-Clamped, Spread-Spectrum,
Current-Mode PWM Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V
V
unless otherwise noted. Typical values are at T
4
GND
AUXDRV DRIVER
Pulldown Impedance
Pullup Impedance
Peak Sink Current
Peak Source Current
Fall Time
Rise Time
DEAD-TIME PROGRAMMING (DT)
DT Bias Voltage
NDRV to AUXDRV Delay
(Dead Time)
CURRENT-LIMIT COMPARATORS (CS)
Cycle-by-Cycle Peak
Current-Limit Threshold
Cycle-by-Cycle Reverse
Current-Limit Threshold
Current-Sense Blanking Time
for Reverse Current Limit
Number of Consecutive Peak
Current-Limit Events to Hiccup
Current-Sense Leading-Edge
Blanking Time
Propagation Delay from
Comparator Input to NDRV
Minimum On-Time
SLOPE COMPENSATION (CSSC)
Slope Compensation Current
Ramp Height
PWM COMPARATOR
Comparator Offset Voltage
Current-Sense Gain
Current-Sense Leading-Edge
Blanking Time
Comparator Propagation Delay
IN
= 12V (for MAX5974A/MAX5974C, bring V
, V
EN
PARAMETER
= +2V, NDRV = AUXDRV = SS = COMP = unconnected, R
t
CSSC-BLANK
t
t
V
CS-BLANK-
V
A
N
CS-BLANK
SYMBOL
V
t
CS-PEAK
R
ON-MIN
PWM-OS
R
CS-PWM
t
CS-REV
HICCUP
t
t
t
AUX-R
PDCS
AUX-F
AUX-N
REV
PWM
AUX-P
V
t
DT
DT
A
IN
= +25NC.) (Note 2)
up to 21V for startup), V
Turns AUXDRV off for the remaining
cycle if reverse current limit is exceeded
From AUXDRV falling edge
From NDRV rising edge
From CS rising (10mV overdrive) to
NDRV falling (excluding leading-edge
blanking)
Current ramp’s peak added to CSSC
input per switching cycle
V
DV
From NDRV rising edge
Change in V
internal leading-edge blanking)
I
I
C
C
From NDRV falling
to AUXDRV falling
AUXDRV rising to
NDRV rising
COMP
AUXDRV
AUXDRV
AUXDRV
AUXDRV
COMP
- V
/DV
(sinking) = 50mA
(sourcing) = 25mA
CSSC
= 1nF
= 1nF
CSSC
CSSC
CONDITIONS
(Note 4)
= 10mV (including
RT
= 34.8kI, R
CS
R
R
R
R
= V
DT
DT
DT
DT
= 10kI
= 100kI
= 10kI
= 100kI
CSSC
DT
= V
= 25kI, C
DITHER/SYNC
-118
1.35
MIN
300
310
375
100
3.1
47
IN
= 1FF, T
= V
1.215
-100
TYP
10.6
3.33
350
360
393
115
115
150
115
150
4.3
0.5
0.3
1.7
24
45
40
40
35
52
8
FB
= V
A
= -40NC to +85NC,
MAX
18.9
FFB
410
420
410
200
7.7
-88
3.6
58
2
= V
DCLMP
UNITS
Events
mV
mV
V/V
FA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I
I
A
A
V
V
=