LC4128V-10TN100I Lattice, LC4128V-10TN100I Datasheet - Page 13
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LC4128V-10TN100I
Manufacturer Part Number
LC4128V-10TN100I
Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer
Lattice
Series
ispMACH®r
Datasheet
1.LC4256V-75TN100I.pdf
(94 pages)
Specifications of LC4128V-10TN100I
Memory Type
EEPROM
Number Of Macrocells
128
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
333 MHz
Delay Time
2.7 ns
Number Of Programmable I/os
64
Operating Supply Voltage
3.3 V
Supply Current
12 mA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-100
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Programmable Type
CPLD
Voltage - Input
3 V ~ 3.6 V
Speed
10ns
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4128V-10TN100I
Manufacturer:
LATTICE
Quantity:
3 660
Company:
Part Number:
LC4128V-10TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4128V-10TN100I
Manufacturer:
LATTICE
Quantity:
20 000
Lattice Semiconductor
Figure 10. Global OE Generation for ispMACH 4032
Zero Power/Low Power and Power Management
The ispMACH 4000 family is designed with high speed low power design techniques to offer both high speed and
low power. With an advanced E
approach), the ispMACH 4000 family offers SuperFAST pin-to-pin speeds, while simultaneously delivering low
standby power without needing any “turbo bits” or other power management schemes associated with a traditional
sense-amplifier approach.
The zero power ispMACH 4000Z is based on the 1.8V ispMACH 4000C family. With innovative circuit design
changes, the ispMACH 4000Z family is able to achieve the industry’s “lowest static power”.
IEEE 1149.1-Compliant Boundary Scan Testability
All ispMACH 4000 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows
functional testing of the circuit board on which the device is mounted through a serial scan path that can access all
critical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port operates with an LVCMOS
interface that corresponds to the power supply voltage.
I/O Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os’
physical nature should be minimal so that board test time is minimized. The ispMACH 4000 family of devices allows
this by offering the user the ability to quickly configure the physical nature of the I/O cells. This quick configuration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
Shared PTOE
(Block 0)
Shared PTOE
(Block 1)
2
low power cell and non sense-amplifier design approach (full CMOS logic
Internal Global OE
(2 lines)
PT Bus
Fuse connection
Hard wired
13
Global OE
Global
Fuses
ispMACH 4000V/B/C/Z Family Data Sheet
Global OE Bus
to I/O cells
GOE (3:0)
4-Bit