LC4128V-10TN144I Lattice, LC4128V-10TN144I Datasheet - Page 37
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LC4128V-10TN144I
Manufacturer Part Number
LC4128V-10TN144I
Description
CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD
Manufacturer
Lattice
Series
ispMACH®r
Datasheet
1.LC4256V-75TN100I.pdf
(94 pages)
Specifications of LC4128V-10TN144I
Memory Type
EEPROM
Number Of Macrocells
128
Number Of Product Terms Per Macro
80
Maximum Operating Frequency
333 MHz
Delay Time
2.7 ns
Number Of Programmable I/os
96
Operating Supply Voltage
3.3 V
Supply Current
12 mA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Programmable Type
CPLD
Voltage - Input
3 V ~ 3.6 V
Speed
10ns
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LC4128V-10TN144I
Manufacturer:
Lattice
Quantity:
108
Company:
Part Number:
LC4128V-10TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
LC4128V-10TN144I
Manufacturer:
LATTICE
Quantity:
20 000
ispMACH 4000Z Timing Adders
Lattice Semiconductor
Optional Delay Adders
t
t
t
t
t
LVTTL_in
LVCMOS33_in
LVCMOS25_in
LVCMOS18_in
PCI_in
t
LVTTL_out
LVCMOS33_out
LVCMOS25_out
LVCMOS18_out
PCI_out
Slow Slew
Note: Open drain timing is the same as corresponding LVCMOS timing.
1. Refer to Technical Note TN 1004, ispMACH 4000 Timing Model Design and Usage Guidelines for information regarding the use of these
INDIO
EXP
ORP
BLA
IOI
IOO
adders.
Input Adjusters
Output Adjusters
Adder
Type
t
t
—
t
t
t
t
t
t
t
t
t
t
t
t
INREG
MCELL
ROUTE
IN,
IN,
IN,
IN,
IN,
BUF,
BUF,
BUF,
BUF,
BUF,
BUF,
t
t
t
t
t
Parameter
GCLK_IN,
GCLK_IN,
GCLK_IN,
GCLK_IN,
GCLK_IN,
t
t
t
t
t
t
EN,
EN,
EN,
EN,
EN,
EN
Base
t
t
t
t
t
DIS
DIS
DIS
DIS
DIS
t
t
t
t
t
GOE
GOE
GOE
GOE
GOE
Input register delay
Product term expander
delay
Output routing pool
delay
Additional block load-
ing adder
Using LVTTL standard
Using LVCMOS 3.3
standard
Using LVCMOS 2.5
standard
Using LVCMOS 1.8
standard
Using PCI compatible
input
Output configured as
TTL buffer
Output configured as
3.3V buffer
Output configured as
2.5V buffer
Output configured as
1.8V buffer
Output configured as
PCI compatible buffer
Output configured for
slow slew rate
Description
1
37
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ispMACH 4000V/B/C/Z Family Data Sheet
-35
Max.
1.00
0.40
0.40
0.04
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-37
Max.
1.00
0.40
0.40
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Min.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-42
Max.
1.30
0.45
0.40
0.05
0.60
0.60
0.60
0.00
0.60
0.20
0.20
0.10
0.00
0.20
1.00
Timing v.2.2
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns