LCMXO640C-5TN144C Lattice, LCMXO640C-5TN144C Datasheet - Page 18

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LCMXO640C-5TN144C

Manufacturer Part Number
LCMXO640C-5TN144C
Description
CPLD - Complex Programmable Logic Devices 640 LUTS 113 I/O
Manufacturer
Lattice
Datasheet

Specifications of LCMXO640C-5TN144C

Memory Type
SRAM
Number Of Macrocells
320
Maximum Operating Frequency
600 MHz
Delay Time
4.9 ns
Number Of Programmable I/os
256
Operating Supply Voltage
1.8 V, 2.5 V, 3.3 V
Supply Current
17 mA
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
3.465 V
Supply Voltage (min)
1.71 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LCMXO640C-5TN144C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Company:
Part Number:
LCMXO640C-5TN144C-4I
Quantity:
1 146
Lattice Semiconductor
Figure 2-16. MachXO PIO Block Diagram
sysIO Buffer
Each I/O is associated with a flexible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are pow-
ered using V
and a V
ers.
MachXO256 and MachXO640 devices contain single-ended input buffers and single-ended output buffers with
complementary outputs on all the I/O Banks.
MachXO1200 and MachXO2280 devices contain two types of sysIO buffer pairs.
1. Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The
PCI clamp is enabled after V
figured.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
CCAUX
CCIO
supply that powers up a variety of internal circuits including all the differential and referenced input buff-
. In addition to the Bank V
Note: Buffer 1 tracks with V
From Routing
From Routing
Fast Output
Data signal
Input
Data Signal
Buffer 2 tracks with V
Buffer 3 tracks with internal 1.2V V
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
CC
, V
CCAUX
CCAUX
CCIO.
CCIO
, and V
Programmable
Delay Elements
supplies, the MachXO devices have a V
REF .
CCIO
2-15
are at valid operating levels and the device has been con-
DO
TS
sysIO
Buffer
4
1
2
3
+
-
From Complementary
Pad
MachXO Family Data Sheet
TO
TSALL
PAD
CC
core logic power supply,
Architecture

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