M4A5-192/96-10VNC Lattice, M4A5-192/96-10VNC Datasheet - Page 10
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M4A5-192/96-10VNC
Manufacturer Part Number
M4A5-192/96-10VNC
Description
CPLD - Complex Programmable Logic Devices HI PERF E2CMOS PLD
Manufacturer
Lattice
Datasheet
1.M4A5-6432-10JNC.pdf
(62 pages)
Specifications of M4A5-192/96-10VNC
Number Of Macrocells
192
Number Of Product Terms Per Macro
20
Maximum Operating Frequency
100 MHz
Delay Time
5 ns
Number Of Programmable I/os
680
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Package / Case
TQFP-144
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Package
144TQFP
Family Name
ispMACHÂ 4A
Device System Gates
7500
Number Of Macro Cells
192
Maximum Propagation Delay Time
10 ns
Number Of User I/os
96
Typical Operating Supply Voltage
5 V
Operating Temperature
0 to 70 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M4A5-192/96-10VNC
Manufacturer:
Lattice
Quantity:
135
Company:
Part Number:
M4A5-192/96-10VNC
Manufacturer:
CITIZEN
Quantity:
7 297
Company:
Part Number:
M4A5-192/96-10VNC
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Part Number:
M4A5-192/96-10VNC
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
M4A5-192/96-10VNC-12VNI
Manufacturer:
LATTICE
Quantity:
67
Company:
Part Number:
M4A5-192/96-10VNC-12VNI
Manufacturer:
LATTICE
Quantity:
7
Macrocell
The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization
control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode
chosen only affects clocking and initialization in the macrocell.
In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will
generally be used, since it provides more product terms in the allocator.
10
From Logic Allocator
From PAL-Block
Clock Generator
Individual Clock
Product Terms
Product Term
Product Term
Initialization
Initialization
From Logic
PAL-Clock
Individual macrocell resources
PAL-Block
Generator
Common PAL-block resource
Individual
Allocator
From
Power-Up
Block CLK0
Block CLK1
Block CLK2
Block CLK3
Block CLK0
Block CLK1
Power-Up
Reset
Reset
ispMACH 4A Family
a. Synchronous mode
b. Asynchronous mode
Figure 5. Macrocell
SWAP
SWAP
D/T/L
D/T/L
AP
AP
AR
AR
Q
Q
To Output and Input
Switch Matrices
To Output and Input
Switch Matrices
17466G-009
17466G-010