AGLN030V5-ZUCG81 Actel, AGLN030V5-ZUCG81 Datasheet - Page 39
AGLN030V5-ZUCG81
Manufacturer Part Number
AGLN030V5-ZUCG81
Description
FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
Manufacturer
Actel
Datasheet
1.AGLN030V5-ZUCG81.pdf
(140 pages)
Specifications of AGLN030V5-ZUCG81
Processor Series
AGLN030
Core
IP Core
Number Of Macrocells
256
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
66
Supply Voltage (max)
1.5 V
Supply Current
6 uA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
30 K
Package / Case
CSP-81
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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The length of time an I/O can withstand I
reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of
analysis.
For example, at 100°C, the short current condition would have to be sustained for more than six months
to cause a reliability concern. The I/O design does not contain any short circuit protection, but such
protection would only be needed in extremely prolonged stress conditions.
Table 2-31 • Duration of Short Circuit Event before Failure
Table 2-32 • Schmitt Trigger Input Hysteresis
Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Temperature
–40°C
–20°C
0°C
25°C
70°C
85°C
100°C
Input Buffer Configuration
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)
2.5 V LVCMOS (Schmitt trigger mode)
1.8 V LVCMOS (Schmitt trigger mode)
1.5 V LVCMOS (Schmitt trigger mode)
1.2 V LVCMOS (Schmitt trigger mode)
Input Buffer
LVTTL/LVCMOS (Schmitt trigger
disabled)
LVTTL/LVCMOS (Schmitt trigger
enabled)
*
The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is
low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The
longer the rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends
signal integrity evaluation/characterization of the system to ensure that there is no excessive noise
coupling into input signals.
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Rise/Fall
No requirement
No requirement
Time (min.)
OSH
R ev i si o n 1 1
/I
OSL
events depends on the junction temperature. The
cannot exceed Schmitt
Input Rise/Fall Time
No requirement, but
input noise voltage
hysteresis.
10 ns *
(max.)
Time before Failure
IGLOO nano Low Power Flash FPGAs
> 20 years
> 20 years
> 20 years
> 20 years
6 months
5 years
2 years
Hysteresis Value (typ.)
240 mV
140 mV
80 mV
60 mV
40 mV
20 years (100°C)
20 years (100°C)
Reliability
2- 25
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