A3P1000-FGG144 Actel, A3P1000-FGG144 Datasheet - Page 23
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A3P1000-FGG144
Manufacturer Part Number
A3P1000-FGG144
Description
FPGA - Field Programmable Gate Array 1M System Gates
Manufacturer
Actel
Datasheet
1.A3P1000-FGG144.pdf
(218 pages)
Specifications of A3P1000-FGG144
Processor Series
A3P1000
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
300
Data Ram Size
147456
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
1000 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A3P1000-FGG144
Manufacturer:
ACT
Quantity:
99
Company:
Part Number:
A3P1000-FGG144
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG144
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
Company:
Part Number:
A3P1000-FGG144I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Part Number:
A3P1000-FGG144I
Manufacturer:
ACTEL/爱特
Quantity:
20 000
Company:
Part Number:
A3P1000-FGG144M
Manufacturer:
BROADCOM
Quantity:
101
Company:
Part Number:
A3P1000-FGG144T
Manufacturer:
ACTEL
Quantity:
30 000
Company:
Part Number:
A3P1000-FGG144T
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3 V LVCMOS Wide Range
2.5 V LVCMOS
1.8 V LVCMOS
1.5 V LVCMOS (JESD8-11)
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. P
3. P
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8b specification.
AC10
DC3
is the static power (where applicable) measured on V
is the total dynamic power measured on V
Applicable to Standard I/O Banks
4
C
LOAD
35
35
35
35
35
(pF)
CC
and V
R e v i s i o n 9
CCI
CCI
VCCI (V)
.
.
3.3
3.3
2.5
1.8
1.5
Static Power
P
DC3
(mW)
–
–
–
–
–
ProASIC3 Flash Family FPGAs
2
1
P
Dynamic Power
AC10
431.08
431.08
247.36
128.46
89.46
(µW/MHz)
2 -9
3