AGLN030V2-ZCSG81 Actel, AGLN030V2-ZCSG81 Datasheet - Page 67

• Manufacturer Part Number: AGLN030V2-ZCSG81
• Description: FPGA - Field Programmable Gate Array 30K System Gates IGLOO nano
• Manufacturer: Actel

Specifications of AGLN030V2-ZCSG81

• Processor Series: AGLN030
• Core: IP Core
• Number Of Macrocells: 256
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 66
• Supply Voltage (max): 1.5 V
• Supply Current: 6 uA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 20 C
• Development Tools By Supplier: AGLN-Nano-Kit, AGLN-Z-Nano-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FLASHPRO 4, FlashPro 3, FLASHPRO LITE
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.2 V
• Number Of Gates: 30 K
• Package / Case: CSP-81
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-80 • Input DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
1.2 V DC Core Voltage
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (negedge)
Data Setup for Input DDR (posedge)
Data Hold for Input DDR (negedge)
Data Hold for Input DDR (posedge)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
J
= 70°C, Worst-Case VCC = 1.14 V
Description
R ev i si o n 1 1
Table 2-7 on page 2-7
IGLOO nano Low Power Flash FPGAs
for derating values.
160.00
0.76
0.94
0.93
0.84
0.00
0.00
1.23
1.42
0.00
0.24
0.19
0.31
0.28
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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