AGL060V5-CSG121 Actel, AGL060V5-CSG121 Datasheet - Page 121

• Manufacturer Part Number: AGL060V5-CSG121
• Description: FPGA - Field Programmable Gate Array 60K System Gates IGLOO
• Manufacturer: Actel

Specifications of AGL060V5-CSG121

• Processor Series: AGL06
• Core: IP Core
• Maximum Operating Frequency: 892.86 MHz
• Number Of Programmable I/os: 96
• Data Ram Size: 18432
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGL-Icicle-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 60 K
• Package / Case: CSP-121
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-172 • AGL015 Global Resource
Table 2-173 • AGL030 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
3. For specific junction temperature and voltage supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
located in a lightly loaded row (single element is connected to the global net).
loaded row (all available flip-flops are connected to the global net in the row).
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
present minimum and maximum global clock delays within each device. Minimum and maximum delays
are measured with minimum and maximum loading.
Timing Characteristics
Commercial-Case Conditions: T
Commercial-Case Conditions: T
1.5 V DC Core Voltage
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
"Clock Conditioning Circuits" section on page
Description
Description
J
J
= 70°C, VCC = 1.425 V
= 70°C, VCC = 1.425 V
R ev i si o n 1 8
2-115.
Table 2-6 on page 2-7
Table 2-6 on page 2-7
Table 2-172
to
IGLOO Low Power Flash FPGAs
for derating values.
for derating values.
Table 2-187 on page 2-114
Min.
Min.
1.21
1.23
1.21
1.23
1
1
Std.
Std.
Max.
Max.
1.42
1.49
0.27
1.42
1.49
0.27
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 107